用于低功率全加法器的多功能亚门限门

Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI:10.1109/NORCHP.2004.1423818

S. Aunet, B. Oelmann, T. Lande, Y. Berg

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引用次数: 7

摘要

本文提出了一种基于实时可重构CMOS感知器电路的全加法器。感知器基于三个输出有线逆变器，通过良好的偏置配置。通过对0.12 um CMOS工艺的仿真验证了全加法器的有效性。在200-400 mV的电源电压下，功能得到了验证。仿真结果表明，Vdd为200 mV时，最小功耗为7.4 nW，功率延迟积为7.8 fJ。

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Multifunction subthreshold gate used for a low power full adder

This paper presents a full-adder based on realtime reconfigurable CMOS perceptron circuits operating in subthreshold. The Perceptron is based on three output wired inverters that is configured through well biasing. The full-adder is demonstrated by simulations for a 0.12 um CMOS process. Functionality is proven for 200-400 mV power supply voltages. Minimum power consumption is 7.4 nW and power-delay-product 7.8 fJ, for a Vdd of 200 mV, according to simulations.

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Proceedings Norchip Conference, 2004.

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