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Proceedings Norchip Conference, 2004.最新文献

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A 1 GHz AGC amplifier in BiCMOS with 3 μ s settling-time for 802.11a WLAN 用于802.11a无线局域网的1 GHz BiCMOS AGC放大器，稳定时间为3 μ s
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423880
K. Schmalz
{"title":"A 1 GHz AGC amplifier in BiCMOS with 3 μ s settling-time for 802.11a WLAN","authors":"K. Schmalz","doi":"10.1109/NORCHP.2004.1423880","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423880","url":null,"abstract":"An analog automatic gain control (AGC) amplifier for application in an 802. I la transceiver with a settling time of 3 μ s within ± I dB limits has been designed and tested. The amplifier operates up to 1.2 GHz and has a linear-in-dB gain control with 63 dB maximum gain, and an AGC range of 45 dB. The AGC detects the averaged signal strength. The circuit includes a fill-wave rectifier and a rail-to-rail difference amplifier. It is fabricated in a 0.25 μm SiCe:C BiCMOS process.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A phase noise analysis of CMOS colpitts oscillators CMOS柯氏振荡器的相位噪声分析
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423845
Xiaoyan Wang, P. Andreani
{"title":"A phase noise analysis of CMOS colpitts oscillators","authors":"Xiaoyan Wang, P. Andreani","doi":"10.1109/NORCHP.2004.1423845","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423845","url":null,"abstract":"This paper presents a closed-form symbolic formula for phase-noise in the 1/f2 region of Colpitts oscillator. Calculations based on the formula are verified by simulations, showing accurate results under general assumptions. A new topology of differential Colpitts is proposed, coupling two single-ended Colpitts oscillators by a center tapped inductor insteod of a common mode capacitor. A comparison of phase noise between the differential Colpitts oscillator and the cross-coupled LC-tank oscillator is carried out, showing the LC-tank oscillator presents a better phase noise, working in the same condition. Several prototypes of both Copitts and cross-coupled oscillators have been implemented in a 0.35μm CMOS process. The best performance of the LC-tank oscillators shows a phase noise of-139dB/Hz at 3MHz offset frequency from a 3GHz carrier with a 10mW power consumption, resulting in an excellent phase noise figure-of-merit (FoM) of 189dBC/Hz. Under the same working conditions, the FoM displayed by the differential Colpitts oscillators is between 4dB and 8dB lower than the FoM displayed by the cross-coupled LC-tank oscillators.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116952295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low-power CMOS front-end for cuff-recorded nerve signals 用于袖带记录神经信号的低功耗CMOS前端
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423813
J. Nielsen, E. Bruun
{"title":"A low-power CMOS front-end for cuff-recorded nerve signals","authors":"J. Nielsen, E. Bruun","doi":"10.1109/NORCHP.2004.1423813","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423813","url":null,"abstract":"A low-power signal sensor front-end for biomedical applications is presented. The front-end consists of a preamplifier and an AID converter (ADC) for quantizing the sensor readout signal. The amplifier achieves low thermal noise by utilizing the weak inversion biasing region of MOSTs and low I/f-noise by chopper modulation. The resulting equivalent input referred noise is 7 nV/Hz, for a chopping frequency of 20 kHz. The implemented gain is 72.5 dB over a signal bandwidth of 4 kHz. The ADC is implemented as a third order ΣΔ-modulator employing a continuous-time (CT) loop filter. The loop filter integrators are implemented as Gm - C elements. The ADC signal-to-noise- and-distortion-ratio (SNDR) is measured to 62 dB, equivalent to 10 bits performance over a 4 kHz bandwidth and a dynamic range (OR) of 67 dB. The systems draws 353 μW of power from a modest supply voltage of 1.8 V.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FPGA based fault emulation of synchronous sequential circuits 基于FPGA的同步时序电路故障仿真
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1049/iet-cdt:20050065
P. Ellervee, J. Raik, K. Tammemäe, R. Ubar
{"title":"FPGA based fault emulation of synchronous sequential circuits","authors":"P. Ellervee, J. Raik, K. Tammemäe, R. Ubar","doi":"10.1049/iet-cdt:20050065","DOIUrl":"https://doi.org/10.1049/iet-cdt:20050065","url":null,"abstract":"This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to further speed up simulation, we propose to make use of reconfigurable hardware by emulating circuit together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A simulation model for embedding the transistor bias 晶体管偏置嵌入的仿真模型
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423863
J. Piper, J. Yuan
{"title":"A simulation model for embedding the transistor bias","authors":"J. Piper, J. Yuan","doi":"10.1109/NORCHP.2004.1423863","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423863","url":null,"abstract":"A simulation model for embedding the bias of a transistor is presented. The model exploits the simulators equilibrium point calculation to set the bias point of the transistor The model uses negative feedback to set the bias point according to what the designer desires. When the simulator goes into its main analyses the negative feedback is broken and embedded bias sources are added. This way it is possible to test an amplifier design before implementing the bias circuits. The model is technology independent can be used on any kind of transistor.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122824016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system 在片上通信系统中通过更好地利用保证吞吐量信道来提高最佳努力吞吐量
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423874
D. Andreasson, S. Kumar
{"title":"On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system","authors":"D. Andreasson, S. Kumar","doi":"10.1109/NORCHP.2004.1423874","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423874","url":null,"abstract":"It is possible to concurrently run multiple applications on IP-core based SoC built using Network on Chip (NoC) paradigm. Some applications require predictable and guaranteed on-chip communication performance. In this paper we propose a new approach for using underutilized reservation of guaranteed throughput (CT) traffic to improve the performance of best effort (BE) traffic. We have modeled our scheme for a mesh topology NoC on a simulation platform. The results show that the proposed scheme leads lo significant improvement in BE performance.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Low-phase-error and low-phase-noise 2GHz CMOS quadrature VCOs 低相位误差和低相位噪声2GHz CMOS正交压控振荡器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423846
Xiaoyan Wang, P. Andreani
{"title":"Low-phase-error and low-phase-noise 2GHz CMOS quadrature VCOs","authors":"Xiaoyan Wang, P. Andreani","doi":"10.1109/NORCHP.2004.1423846","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423846","url":null,"abstract":"This paper presents a low-phase-error and low-phase-noise quadrature-voltage-control-oscillator (Q VCO). The mutual inductance effect, which has a very severe effect on the phase-error performance, is minimized by implementing a new layout design. The losses of the tank are also minimized since a more compact layout is achieved. The QVCOs were implemented in a standard CMOS 0.35μ process. The center frequency is 2GHz, and the tuning range is 15%. The new implementation presents a 45dB image-band-rejection (IBR) ratio and the phase noise measured is -140dBc at 3MHz offset frequency, with a QVCO core power dissipation of 32mW at 2V power supply.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-power reconfigurable baseband block for UMTS/WLAN transmitters 用于UMTS/WLAN发射机的低功耗可重构基带块
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423833
S. D’Amico, A. Baschirotto, A. Vigna, N. Ghittori, P. Malcovati
{"title":"Low-power reconfigurable baseband block for UMTS/WLAN transmitters","authors":"S. D’Amico, A. Baschirotto, A. Vigna, N. Ghittori, P. Malcovati","doi":"10.1109/NORCHP.2004.1423833","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423833","url":null,"abstract":"A low-power reconfigurable analog baseband block for UMTS/WLAN transmitters is presented. The law-power pe6ormance is guaranteed by the innovative architecture that allows to directly connect the output DAC current with the reconstruction analog filter. The DAC and the baseband filter, have been designed in a 0.13pm CMOS technology with a power supply limited to I.2K The current consumption, has been optimized for the selected UMTS or WLAN standard and it equal to 7.9mA and 10mA, respectively.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A variable word-width content addressable memory for fast string matching 用于快速字符串匹配的可变字宽内容可寻址存储器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423861
G. Nilsen, J. Tørresen, Oddvar Ssrhen
{"title":"A variable word-width content addressable memory for fast string matching","authors":"G. Nilsen, J. Tørresen, Oddvar Ssrhen","doi":"10.1109/NORCHP.2004.1423861","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423861","url":null,"abstract":"This work deals with off-boding some time critical parts in the process of performing intrusion detection from software to reconfigurable hardware (FPGA). Signatures of known attacks must typically be compared to high speed network traffic, and string matching becomes a bottleneck Content Addressable Memories (CAMS) are known to be fast string matchers, but offer little flexibility. For that purpose a Variable Word- Width CAM for fast string matching has been designed and implemented in an FPGA A typical feature for this CAM is that the length of each word is independent from the others, in contrast to common CAMs where all words have the same length. The design has been functionally tested on a development board for a CAM of size 1822 bytes (128 words). This design processes 8 bits per clock cycle and has a reported maximum clock speed of 100 MHL This gives a thoughput of 800 Mbit/s.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131943727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Formal timing model for hardware components 硬件组件的正式定时模型
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423881
T. Westerlund, J. Plosila
{"title":"Formal timing model for hardware components","authors":"T. Westerlund, J. Plosila","doi":"10.1109/NORCHP.2004.1423881","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423881","url":null,"abstract":"The correctness of functional and non-functional properties of hardware components is ensured during development cycles conventionally by simulation. Also different description languages are needed during development phases. With Action Systems, we are able to use the same formalism from a speci cation down into an implementation. In this study we present timed Action Systems, an extension of Action Systems, with which a non-functional property, time, can be modelled. We show how untimed models are transformed into timed ones, and how timing characteristics of a model are analysed.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131947294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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