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Proceedings Norchip Conference, 2004.最新文献

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Phase noise analysis of the LC-tank CMOS oscillator LC-tank CMOS振荡器相位噪声分析
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423844
Pietro Andreani
{"title":"Phase noise analysis of the LC-tank CMOS oscillator","authors":"Pietro Andreani","doi":"10.1109/NORCHP.2004.1423844","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423844","url":null,"abstract":"This paper presents a phase noise analysis of the very popular differential LC-tank CMOS oscillator. Closed-forms formulas for the phase noise in the 1/f2 region are derived under very general assumptions.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysis method of nonlinear self-heating ef fects based on simulated large signal spectra 基于模拟大信号谱的非线性自热效应分析方法
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423830
J. Aikio, T. Rahkonen
{"title":"Analysis method of nonlinear self-heating ef fects based on simulated large signal spectra","authors":"J. Aikio, T. Rahkonen","doi":"10.1109/NORCHP.2004.1423830","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423830","url":null,"abstract":"In this paper the harmonic balance is used to simulate the large signal I-V spectra of the intrinsic simulation model that are further used to fit a 3-dimensional electro-thermal polynomial model of the IDS - VDS - VGS nonlinearity. The fitted model is used to analyse the amount of self-heating distortion. To get reliable results a correct model for the thermal circuit of the simulation model is required. Also. strongly correlating control signals cause the system to be difficult to solve. To reliably the IDS different test setups need to be considered.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134561392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology 基于CMOS技术的CALLUM 2发射机结构信号分量发生器的实现
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423853
R. Strandberg, P. Andreani, L. Sundstrom
{"title":"Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology","authors":"R. Strandberg, P. Andreani, L. Sundstrom","doi":"10.1109/NORCHP.2004.1423853","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423853","url":null,"abstract":"This article presents an analog implementation of the signal component generator (SCG) of the CALLUM 2 linear transmitter architecture. The proposed SCG is suited for integration in a standard 0.35 μ m CMOS process, and has from simulations proven to be adequate when operating on an EDGE modulated baseband signal with a data rate of 270.833 ksymb/s. The total current consumption of the SCG is 2.0mA from a 3.3 V supply. A variable gain amplifier (VGA) with common-mode (CM) control is presented, and the VGA is inserted in between the SCG and the voltage-controlled oscillator (VCO) to adjust the loop gain, which has strong influence on the stability and spectral performance of the linear transmitter architecture.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"426 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123007443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Σ Δ fractional-N closed-loop modulator for DECT 用于DECT的Σ Δ分数n闭环调制器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423856
D. Hermansen, E. Buskgaard, P. Olesen, F. Andreasen, T. Larsen
{"title":"A Σ Δ fractional-N closed-loop modulator for DECT","authors":"D. Hermansen, E. Buskgaard, P. Olesen, F. Andreasen, T. Larsen","doi":"10.1109/NORCHP.2004.1423856","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423856","url":null,"abstract":"Traditionally, modulators for DECT are implemented using open-loop modulation. However: open-loop modulators are too slow for 100% slot utilization. This causes the well known DECT blind-slot problem. One solution to this is to employ closed-loop modulation in stead. This paper presents a closed-loop modulator solution for DECI: The modulator b based on a combination of ΣΔ-techniques and use of a fractional-N PLL. The technique allows for digital phase and frequency modulation without use of mixers or D/A converters in the modulation path. Simulation results show a working modulator that is superior to state-of-the-art DECT transmitters using open-loop modulation. An internal reference frequency of 10 - 30 MHz gives an output PSD that meets DECT speci cation requirements on unwanted emissions due to modulation. The RMS phase error for a reference frequency of 31.104 MHz is as low as 1.06° and the peak phase error is 2.90°. The blind-slot problem is solved using the closed-loop modulator as the lock time is 1 - μs which, compared to the guard space requirements of below 50 μ, gives a large room for implementation imperfections.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131772630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A method of varactor capacitance modulation reduction in CMOS LC-VCOs CMOS lc - vco变容电容调制减小方法
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423835
D. Kokotovic
{"title":"A method of varactor capacitance modulation reduction in CMOS LC-VCOs","authors":"D. Kokotovic","doi":"10.1109/NORCHP.2004.1423835","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423835","url":null,"abstract":"A method of varactor capacitance modulation reduction is proposed based on the varactor elements with different degrees of nonlinearity. Two fully integrated LC-voltage-controlled oscillators (VCOs) were fabricated in CMOS technology. VCO1 has a traditional varactor configuration whereas VCO2 utilized the proposed linearization method. VCO2 exhibits an average of 10 dB phase noise improvement at 100 kHz offset across the tuning range around a 4 GHz carrier. Each VCO consumes 20 mA at 1.8 V supply voltage.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130833048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new class of linear-phase FIR filters based on switching and resetting of IIR filters 一种基于IIR滤波器开关复位的新型线性相位FIR滤波器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423849
P. Arian, T. Saramaki, A. Fam
{"title":"A new class of linear-phase FIR filters based on switching and resetting of IIR filters","authors":"P. Arian, T. Saramaki, A. Fam","doi":"10.1109/NORCHP.2004.1423849","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423849","url":null,"abstract":"A class of linear-phase FIR lters was originally introduced by the last two authors of this article. Their proposed structure approximated the transfer function of G(z)G(z-1), where G(z) was the transfer function of a Stable IIR lter. The approximation to G(z)G(z--1) was essentially a truncation of its impulse response performed by a feed forward part, followed by a shift to make it implementable. This paper introduces a new approximation to G(z)G(z-1), based on an alternative truncation scheme, and discusses its advantages over the original design.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation 16 GSPS 0.18 μm CMOS单位十进制器Σ Δ-modulation
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423851
H. Ohlsson, B. Mesgarzadeh, K. Johansson, O. Gustafsson, P. Lowenborg, H. Johansson, A. Alvandpour
{"title":"A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation","authors":"H. Ohlsson, B. Mesgarzadeh, K. Johansson, O. Gustafsson, P. Lowenborg, H. Johansson, A. Alvandpour","doi":"10.1109/NORCHP.2004.1423851","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423851","url":null,"abstract":"In this work an implementation of a high-speed decimation Iter for single-bit Σ Δ -modulators is presented. The presented chip is designed in a 0.18 μm CMOS process for 16 GSamples/s with four parallel 4GSamples/s inputs. The 1- tering consists of two stages. After a 1-to-8-demuItiplexer, the rst stage employs a novel architecture and work at a clock frequency of 0.5 GHz while providing a decimation by a factor of 32. In the second stage the remaining decimation by a factor of 4 is performed. A downscaled version with a total decimation of 64 for a 8 GSamples/s Σ Δ -modulator is also included on the chip.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An improved estimation methodology for hybrid BIST cost calculation 一种改进的混合BIST成本估算方法
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423882
G. Jervan, Zebo Peng, R. Ubar, Olga Korelina
{"title":"An improved estimation methodology for hybrid BIST cost calculation","authors":"G. Jervan, Zebo Peng, R. Ubar, Olga Korelina","doi":"10.1109/NORCHP.2004.1423882","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423882","url":null,"abstract":"This paper presents an improved estimation methodology for hybrid BIST cost calculation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is largely determined by the ratio of those test patterns in the final test set. Unfortunately exact algorithms for finding the test sets are computationally very expensive. Therefore in this paper we propose an improved estimation methodology for fast calculation of the hybrid test set. The methodology is based on real fault simulation results and experimental results have shown that the method is more accurate than the statistical method proposed earlier.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Injection locked coupled VCOs for low phase noise and high accuracy quadrature generation 用于低相位噪声和高精度正交生成的注入锁相耦合压控振荡器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423820
A. Mazzanti, P. Uggetti, F. Svelto
{"title":"Injection locked coupled VCOs for low phase noise and high accuracy quadrature generation","authors":"A. Mazzanti, P. Uggetti, F. Svelto","doi":"10.1109/NORCHP.2004.1423820","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423820","url":null,"abstract":"Coupled VCOs for quadrature generation allow very accurate 90° phase shifted output signal but suffer from a trade-off between phase noise and phase accuracy, leading to poor noise times power product. In this work, we propose to synchronize them by means of an additional VCO. In this way, the coupled VCOs guarantee the quadrature accuracy between output signals, whereas the synchronizing VCO sets phase noise. The design is tailored to a DCS-1800 system. Prototypes, realized in a 0.18μm CMOS technology, show the following: 285MHz tuning band, 45dB minimum Image Band Rejection, -127 dBc/Hz Phase Noise at 600kHz offset while drawing 10mA from 1.8V. The Phase Noise figure of merit is 185dB, 20dB better than free running quadrature VCOs.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flit ejection in on-chip wormhole-switched networks with virtual channels 带虚拟信道的片上虫孔交换网络中的飞动弹射
Proceedings Norchip Conference, 2004. Pub Date : 1900-01-01 DOI: 10.1109/norchp.2004.1423876
Zhonghai Lu, A. Jantsch
{"title":"Flit ejection in on-chip wormhole-switched networks with virtual channels","authors":"Zhonghai Lu, A. Jantsch","doi":"10.1109/norchp.2004.1423876","DOIUrl":"https://doi.org/10.1109/norchp.2004.1423876","url":null,"abstract":"An ideal it-ejection model is typically assumed in the Literature for wormhole switches with virtual channels. With such a model its are ejected from the network immediately upon reaching their destinations. This achieves optimal performance but is very costly. The required number of sink queues of a switch for absorbing its is p . v, where p is the number of physical channels (PCs) of the switch; v the number of lanes per PC. To achieve cheap silicon implementations, it-ejection solutions must be cost-effective. We present a novel it-ejection model and a variant of it where the required number of sink queues of a switch is p, i.e., independent of v. We evaluate the it-ejection models with uniformly distributed random traffic in a ZD mesh network. Experimental results show that they exhibit good performance in latency and throughput.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128990502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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