A 16 GSPS 0.18 μm CMOS decimator for single-bit Σ Δ-modulation

Abstract

In this work an implementation of a high-speed decimation Iter for single-bit Σ Δ -modulators is presented. The presented chip is designed in a 0.18 μm CMOS process for 16 GSamples/s with four parallel 4GSamples/s inputs. The 1- tering consists of two stages. After a 1-to-8-demuItiplexer, the rst stage employs a novel architecture and work at a clock frequency of 0.5 GHz while providing a decimation by a factor of 32. In the second stage the remaining decimation by a factor of 4 is performed. A downscaled version with a total decimation of 64 for a 8 GSamples/s Σ Δ -modulator is also included on the chip.