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Proceedings Norchip Conference, 2004.最新文献

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An analog current-mode 2-D DCT implementation 模拟电流模式二维DCT实现
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423869
M. Pankaala, J. Poikonen, L. Vesalainen, A. Paasio
{"title":"An analog current-mode 2-D DCT implementation","authors":"M. Pankaala, J. Poikonen, L. Vesalainen, A. Paasio","doi":"10.1109/NORCHP.2004.1423869","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423869","url":null,"abstract":"In this paper the rst measurements results of an analog current-mode 2-D DCT test chip are presented. The circuit performs 4-point transform and the measured results con rm the correct operation of the circuit. Moreover, the accuracy of the results is on acceptable level and ful I the imposed requirements in this respect.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127057862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.6 v 1.6 mW fully integrated voltage- controlled oscillator in 90 nm CMOS aiming for the GPS L1 band 一个0.6 v 1.6 mW全集成电压控制振荡器在90纳米CMOS瞄准GPS L1波段
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423819
L. Aspemyr, D. Linten
{"title":"A 0.6 v 1.6 mW fully integrated voltage- controlled oscillator in 90 nm CMOS aiming for the GPS L1 band","authors":"L. Aspemyr, D. Linten","doi":"10.1109/NORCHP.2004.1423819","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423819","url":null,"abstract":"A fully integrated 0.6 V 2.6 mA VCO aimed for the GPS L1 band is realized in a 90 nm CMOS process. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. The VCO has a measured phase noise of-103 dBc/Hz at 100kHz offset and a chip area of 1.15mm2, including bond pads.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient image filtering and information reduction in reconfigurable logic 可重构逻辑中有效的图像滤波和信息缩减
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423823
J. Tørresen, J. W. Bakke, L. Sekanina
{"title":"Efficient image filtering and information reduction in reconfigurable logic","authors":"J. Tørresen, J. W. Bakke, L. Sekanina","doi":"10.1109/NORCHP.2004.1423823","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423823","url":null,"abstract":"An automatic sign detection system could be important in enhancing traffic safety. Such a system would have to be able to provide high speed processing in its real-time environment. In this paper, we show how one of the time consuming parts of a speed limit detection algorithm can be implemented in reconfigurable logic to speed up the processing. Results indicate that the present system would be able to handle 12 images per second.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124157263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A low power, propagation delay stable, continuous-time comparator 低功率，传播延迟稳定，连续时间比较器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423873
Kirill Kozmin, J. Johansson, J. Delsing
{"title":"A low power, propagation delay stable, continuous-time comparator","authors":"Kirill Kozmin, J. Johansson, J. Delsing","doi":"10.1109/NORCHP.2004.1423873","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423873","url":null,"abstract":"This paper describes a design strategy towards a low power, DC level insensitive comparator with stable propagation time. The comparator is must suitable in applications were a constant propagation delay is critical, such as level crossing detection in ultrasound measurements and time quantization A/D converters. The use of a long absolute propagation delay allows low power consumption while keeping the Signal dependent propagation delay variation low. The comparator is able to process signals with all DC level within power rails due to a constant-gm, rail-to-rail, single-ended to differential converter implemented in the input stage. Schematic simulations show that the comparator has less than 1 ns delay variation at an absolute propagation delay of 12 ns. Test signals include frequencies from 0.5 MHz to 10 MHz, amplitudes from 30 mV to 1 V and all DC levels within rails.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114771004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design criteria for the RF section of long range passive RFID systems 远距离无源射频识别系统射频部分设计准则
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423834
G. de Vita, G. Lannaccone
{"title":"Design criteria for the RF section of long range passive RFID systems","authors":"G. de Vita, G. Lannaccone","doi":"10.1109/NORCHP.2004.1423834","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423834","url":null,"abstract":"We have derived a set of consistent design criteria for the RF section of long range passive RFID transponders, operating in the 916 MHz and 2.45 GHz ISM frequency ranges. In particul.ar, we describe the design criteria for the voltage multiplier, for the power matching network between the antenna and the non linear circuit represented by the voltage multiplier, and for the modulator of the backscattered radiation. We discuss the various design tradeoffs and determine the regions of the design space that allow us to maximize the operating range of the RFlD system.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123720748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies 通道长度作为深亚微米CMOS技术中低噪声宽带LNAs的设计参数
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423838
S. Andersson, C. Svensson
{"title":"Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies","authors":"S. Andersson, C. Svensson","doi":"10.1109/NORCHP.2004.1423838","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423838","url":null,"abstract":"In this paper, measurements of drain thermal noise for three NMOS devices with different channel lengths was carried out. The three NMOS devices were all implemented in a 0.18 μm CMOS technology, with channel lengths 0.18. 0.36, and 0.72 μm, respectively. The result was then compared with simulated data using the BSIM3- model and parameters provided by the vendor Large discrepancies between measurements and simulations were observed. This work was done in order to understand how to utilize transistor length as a design parameter to achieve optimal noise gures for wideband LNAs in deep submicron technologies.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1948 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel approach for implementation of adaptive learning rate neural networks 一种实现自适应学习率神经网络的新方法
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423827
M.G. Rezaie, F. Farbiz, E.Z. Moghaddam, A. Hooshmand
{"title":"A novel approach for implementation of adaptive learning rate neural networks","authors":"M.G. Rezaie, F. Farbiz, E.Z. Moghaddam, A. Hooshmand","doi":"10.1109/NORCHP.2004.1423827","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423827","url":null,"abstract":"In this paper hardware implementation of adaptive learning rate neural networks is studied. Same design guidelines are presented to improve integration of learning algorithm into the hardware. By using them, it is possible to design more robust artificial neural networks which are capable of handling a learning algorithm in analog chips. According to the proposed technique, a design area for selecting the best hardware characteristic is obtained by performing evolutionary algorithms.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134565815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS analog integrated circuit for actuation and readout of a MEMS CO2 sensor 用于驱动和读出MEMS CO2传感器的CMOS模拟集成电路
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423814
Alf-Egil Edvardsen, Andreas, Bertil, Trond Ytterdal
{"title":"A CMOS analog integrated circuit for actuation and readout of a MEMS CO2 sensor","authors":"Alf-Egil Edvardsen, Andreas, Bertil, Trond Ytterdal","doi":"10.1109/NORCHP.2004.1423814","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423814","url":null,"abstract":"In this paper, we describe a system for actuation and readout of a MEMS CO2 sensor based on a CMOS Analog Integrated Circuit. Typically, in such sensor system, two separate systems provide both the actuation and readout. This paper presents a system using one single PLL performing both task. This work extends the sensor system described in [1] and [2] and is motivated out of a low-cost and miniaturizing perspective. A protorype has been implemented, that verifies the concept and shows the possibilities of making a small and integrated CO2 sensor system.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121348096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A UML pro le for the TACO protocol processing platform TACO协议处理平台的UML流程
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423864
D. Truscan
{"title":"A UML pro le for the TACO protocol processing platform","authors":"D. Truscan","doi":"10.1109/NORCHP.2004.1423864","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423864","url":null,"abstract":"The Uni ed Modeling Language (UML) gained increased popularity in recent years for system speci cation. Although intended for software development, UML. cm also bring bene ts to hardware speci cation especially for integration of hardware based platforms with UML methodologies and tools. In this paper we intend to evaluate the bene ts of extending UML to model hardware components and we de ne a UML pro le for a protocol processing platform.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127419058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An inductorless peaking technique applied to MOS current-mode logic gates 应用于MOS电流模逻辑门的无电感峰值技术
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423816
S. Badel, Y. Leblebici
{"title":"An inductorless peaking technique applied to MOS current-mode logic gates","authors":"S. Badel, Y. Leblebici","doi":"10.1109/NORCHP.2004.1423816","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423816","url":null,"abstract":"A novel inductorless peaking technique is demonstrated to improve the time-domain response of MOS current mode logic (MCML) gates. The proposed circuit design occupies signi-cantly less area compared to passive inductive peaking solutions, and achieves a speed increase of up to 17% in detailed post-layout simulations, and up to 8.5% in experimental validation. Sample circuits designed using a standard 0.18 μm CMOS technology with 1.8 V power supply exhibit propagation delay times of about 35ps, which allows reliable circuit operation at GHz range clock frequency. The circuit technique discussed here is suitable for cell-bared high-density logic designs.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114380381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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