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Proceedings Norchip Conference, 2004.最新文献

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Comparison of different class-D power amplier topologies for 1-bit band-pass delta-sigma D/A converters 1位带通δ - σ D/A转换器中不同D类功率放大器拓扑结构的比较
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423836
J. Sommarek, A. Virtanen, J. Vankka, K. Halonen
{"title":"Comparison of different class-D power amplier topologies for 1-bit band-pass delta-sigma D/A converters","authors":"J. Sommarek, A. Virtanen, J. Vankka, K. Halonen","doi":"10.1109/NORCHP.2004.1423836","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423836","url":null,"abstract":"The suitabilities of two different class-D power ampli er architectures for I-bit bandpass ΔΣ D/A converters operating with RF signals are compared. The objective is to nd out which architecture provides the best ef ciency. The architectures considered are H-bridge voltage-mode class-D ampli er and transformer-coupled voltage-mode class-D ampli er. These architectures are compared by APLAC simulation using a ΔΣ modulated signal and by measuring discrete component GaAs MESFET realisations.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip 异步片上网络中保证带宽的虚拟信道设计
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423875
T. Bjerregaard, J. Sparsø
{"title":"Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip","authors":"T. Bjerregaard, J. Sparsø","doi":"10.1109/NORCHP.2004.1423875","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423875","url":null,"abstract":"Logically separate channels sharing a physical link, so called virtual channels (VCs), have wide spread uses in multicomputer networks as well as in Network-on-Chip (NoC). This paper presents a number of low overhead VC Implementations, using asynchronous circuit techniques. The designs are highly modular, and can be used to provide access to any shared media. As a demonstration of use, on-chip links providing per connection bandwidth guarantees were implemented.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Power consumption estimation of the multi-threaded xinc processor 多线程xinc处理器的功耗估算
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423860
Y. Le Moullec, C. Leroux, E. Baud, P. Koch
{"title":"Power consumption estimation of the multi-threaded xinc processor","authors":"Y. Le Moullec, C. Leroux, E. Baud, P. Koch","doi":"10.1109/NORCHP.2004.1423860","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423860","url":null,"abstract":"This paper deals with the estimation of the power consumption of embedded system. Recently multithreaded processors have emerged as a viable solution for implementing wireless embedded applications. The main objective of this work is to provide the designer of such system with a fast and reliable method to compare the power consumption of algorithms executing on the multi-threaded Xinc processor. For this purpose, we adapt the existing DSP-dedicated FLPA method to the Xinc processor and devise a model which rapidly provides the power consumption of an algorithm with a maximum error of 2,63x %.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114184542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementation experiments of analog nonvolatile memory with a standard 0.35 μ m CMOS 模拟非易失性存储器在标准0.35 μ m CMOS上的实现实验
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423825
A. Rantala, M. Sopanen, M. Åberg
{"title":"Implementation experiments of analog nonvolatile memory with a standard 0.35 μ m CMOS","authors":"A. Rantala, M. Sopanen, M. Åberg","doi":"10.1109/NORCHP.2004.1423825","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423825","url":null,"abstract":"This paper presents a study upon implementation of a nonvolatile memory with a standard CMOS process. The main emphasis is to obtain an analog, continuous value, EEPROM module. The accuracy, reliability and reproducibility performance of the different memory cells have been investigated. Different types of programming method have been tested and compared EEPROM cells have been processed with two different 0.35 μm CMOS processes and two different process runs. Measurement results show that a reliable, medium accuracy, analog EEPROM can be implemented without any process Modifications.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An analysis of the embedded system design space and two case studies, replacing uP's with an FPGA 分析了嵌入式系统的设计空间和两个案例研究，用FPGA代替uP
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423824
S. Sjoholm, S. Stjemen
{"title":"An analysis of the embedded system design space and two case studies, replacing uP's with an FPGA","authors":"S. Sjoholm, S. Stjemen","doi":"10.1109/NORCHP.2004.1423824","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423824","url":null,"abstract":"This paper first presents an analysis of the embedded system design space. Two case studies are then presented. The first case study shows how several UPS can be replaced by one FPGA in an automobile application, not only improving performance, but also reducing cost, time to market and other important constraints. In the second case study, one UP was replaced by an FPGA to lower cost and power consumption. The FPGA design included a behavioral controller. The behavioral controller is a design technique used when replacing a UP with an FPGA. The behavioral controller is designed in VHDL at RT-level to handle all scheduling, allocation and different forms of pipelining in the FPGA. This method results in a very small, cost effective, high performance FPGA.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131605342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ring road NoC architecture 环路NoC建筑
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423811
H. Samuelsson, S. Kumar
{"title":"Ring road NoC architecture","authors":"H. Samuelsson, S. Kumar","doi":"10.1109/NORCHP.2004.1423811","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423811","url":null,"abstract":"A network of routers on a chip which allows packet switched communication, referred as Networks on Chip (NoC). provides a scalable interconnection architectural option for rapid development of Sacs. In this paper we describe a new NoC architecture. called Ring Road NoC (R2NoC), which was motivated by smooth flow of traffic in interconnected ring roads. Router design and routing algorithm for R2NoC is much simpler. We have developed a SystemC model of R2NoC and our simulation studies demonstrate that the proposed architecture leads to smooth and evenly distributed flow of communication traffic.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130881270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A DC-13GHz LNA for UWB RFID applications 一种用于UWB RFID应用的DC-13GHz LNA
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423868
X. Duo, T. Torikka, Lirong Zheng, M. Ismail, H. Tenhunen, E. Tjukanoff
{"title":"A DC-13GHz LNA for UWB RFID applications","authors":"X. Duo, T. Torikka, Lirong Zheng, M. Ismail, H. Tenhunen, E. Tjukanoff","doi":"10.1109/NORCHP.2004.1423868","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423868","url":null,"abstract":"In this paper, we present a 4-stage traveling wave low noise amplifier for UWB RFID (ultra-wideband radio frequency identification). This LNA covers a frequency range of DC - 13 CHz. The circuit is implemented with 0.15μm GaAs PHEMT chips embedded in flexible LCP (liquid crystal polymer) substrate. In the frequency range, the gain of the LNA is better than IO dB, fluctuation of the gain is less than 3dB, its noise figure is less than 4dB, S11 and S22 are around -10 dB.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134422407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
μ spider: a CAD tool for efficient NoC design μ spider:用于高效NoC设计的CAD工具
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423862
S. Evain, J. Diguet, D. Houzet
{"title":"μ spider: a CAD tool for efficient NoC design","authors":"S. Evain, J. Diguet, D. Houzet","doi":"10.1109/NORCHP.2004.1423862","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423862","url":null,"abstract":"In this paper, we present a generic router and a tool that allow the designer to easily and quickly customise a NoC in order to meet the requirements of a set of applications. Our router addresses what we consider as the main features of a realistic and useful NoC. Firstly, it supports the management of different levels quality of service (QoS) allowing guaranteed throughput service in addition to the classical best effort service. Secondly, it is associated to a CAD tool, which can fully configure and generate the NoC VHDL code at the RTL level. The paper presents the muter architecture and its various custom characteristics as well as their impacts on the performance of the system.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133150461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
High-speed on-chip interconnect modeling for circuit simulation 用于电路仿真的高速片上互连建模
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423843
Peter Caputa, A. Alvandpour, Christer Svensson
{"title":"High-speed on-chip interconnect modeling for circuit simulation","authors":"Peter Caputa, A. Alvandpour, Christer Svensson","doi":"10.1109/NORCHP.2004.1423843","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423843","url":null,"abstract":"We investigate the relevance of inductance in interconnect models through simulation of an on-chip bus described by a HSPICE W-element, a RLC-network, and a RC-network, respectively. For worst-case delay estimations, we show that the simplest RC-model h sufficient. We further demonstrate the importance of including inductance in noise and edge-rate simulations. For the longest interconnect investigated, the W-element and RC-network differ by 20.6% in overshoot, 156% in ground noise, 53.2% in crosstalk and 61.7% in edge-rule simulations. The W-element and RLC-network never diverge by more than 2% in overshoot, 12.4% in ground noise, 8.9% in crosstalk and 5.6% in edge-rate simulations.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116665925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Integrated time counter with 200 ps resolution 集成时间计数器200 ps分辨率
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423859
R. Szymanowski, J. Kalisz
{"title":"Integrated time counter with 200 ps resolution","authors":"R. Szymanowski, J. Kalisz","doi":"10.1109/NORCHP.2004.1423859","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423859","url":null,"abstract":"The integrated time counter on a single CMOS FPGA device is presented. A 200 ps resolution has been achieved in the measurement range 0 - I67 ms utilizing two-stage interpolation method. The maximum integral non-linearity of the embedded time-to-digital converters is 312ps. After correction of the linearity error the standard measurement uncertainty below 140ps was obtained. The Delay-Locked Loop (DLL) was used for indirect time stabilization of the delay elements.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122179665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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