A modified shield-based test fixture for silicon-on-insulator (SOI) to mitigate the uncertainties of the parallel parasitics

Abstract

A modified ground-shielded test fixture is proposed to mitigate the discrepancies of the conventional ground-shielded test future caused by the variation of the vertical oxide thickness. In-situ calibration and immitance correction require that the probe tip to device under test (DUT) area -transition is identical in every test fixture. By employing the proposed test fixture, reduced parasitic uncertainty between test fixtures can he achieved while the capacitive signal loading is significantly decreased while the good isolation properties are remained.