Multifunction subthreshold gate used for a low power full adder

Abstract

This paper presents a full-adder based on realtime reconfigurable CMOS perceptron circuits operating in subthreshold. The Perceptron is based on three output wired inverters that is configured through well biasing. The full-adder is demonstrated by simulations for a 0.12 um CMOS process. Functionality is proven for 200-400 mV power supply voltages. Minimum power consumption is 7.4 nW and power-delay-product 7.8 fJ, for a Vdd of 200 mV, according to simulations.