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Proceedings Norchip Conference, 2004.最新文献

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Dynamic element matching in decomposed digital-to-analog converters 分解数模转换器中的动态元件匹配
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423854
K. Andersson, M. Vesterbacka
{"title":"Dynamic element matching in decomposed digital-to-analog converters","authors":"K. Andersson, M. Vesterbacka","doi":"10.1109/NORCHP.2004.1423854","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423854","url":null,"abstract":"A dynamic element matching (DEMJ technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DAG) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed convener architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90 % yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
13.5 MHz class-S modulator for an EER transmitter 用于EER发射机的13.5 MHz s类调制器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423871
V. Saari, P. Juurakko, J. Ryyndnen, K. Halonen
{"title":"13.5 MHz class-S modulator for an EER transmitter","authors":"V. Saari, P. Juurakko, J. Ryyndnen, K. Halonen","doi":"10.1109/NORCHP.2004.1423871","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423871","url":null,"abstract":"An integrated 13.5MHz class-S modulator for an EER transmitter is described. The modulator uses 3.3 V supply voltage and was fabricated using 0.18 μm CMOS technology. The measured output power was 22.8 dBm for a 10 MHz rectangle pulse input signal with 50% Ye duty cycle. The chip area is 1.6 mm2.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Power analysis of high throughput pipelined carry-propagation adders 高通量流水载波传输加法器的功率分析
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423842
A. Åslund, O. Gustafsson, H. OhIsson, L. Wanhammar
{"title":"Power analysis of high throughput pipelined carry-propagation adders","authors":"A. Åslund, O. Gustafsson, H. OhIsson, L. Wanhammar","doi":"10.1109/NORCHP.2004.1423842","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423842","url":null,"abstract":"In several previous papers the area, delay, and power consumption for various carry-propagation adders have been compared. However, for high throughput applications it may be necessary to introduce pipelining into the adder. The number of stages to be inserted and the width of the pipelining registers differs between different adders structure. In this work we focus on the power consumption far adder structures when pipelining is used to increase the throughput. Four adder structures with varying wordlengths and pipeline levels are implemented using standard cells and the power consumption is compared. The results show that the Kogge-Stone parallel Prefix adder gives the lowest power consumption given the throughput most of the time.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127221351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A linear capacitive sensor interface circuit with single-ended to differential output capability 具有单端对差分输出能力的线性电容式传感器接口电路
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423815
T. Singh, T. Saether, T. Yitterdal
{"title":"A linear capacitive sensor interface circuit with single-ended to differential output capability","authors":"T. Singh, T. Saether, T. Yitterdal","doi":"10.1109/NORCHP.2004.1423815","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423815","url":null,"abstract":"In this paper we present a concept for single-ended to differential capacitive sensor interface circuit suitable for implementation in CMOS. The interface circuit converts the capacitance change of a single sensor capacitor into a differential output voltage. The main advantages of the proposed circuit are high linearity, immunity from parasitic capacitances of the sensor capacitor, and sensitivity to the capacitance change rather than the absolute capacitance.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"504 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121699099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of a self-timed asynchronous parallel FIR filter using CSCD 用CSCD实现自定时异步并行FIR滤波器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423858
H. Lampinen, P. Perala, O. Vainio
{"title":"Implementation of a self-timed asynchronous parallel FIR filter using CSCD","authors":"H. Lampinen, P. Perala, O. Vainio","doi":"10.1109/NORCHP.2004.1423858","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423858","url":null,"abstract":"This work presents various implementation issues of the self-timed asynchronous parallel finite impulse response (F1R) filter. The main objective was to design all the necessary operational blocks using VHDL and commercial electronic design automation (EDA) tools in order to prove that asynchronous current-sensing completion detection (CSCD) circuits can be designed with traditional EDA tools targeted originally for synchronous designs. In order to make the design steps more effective, some improvements for the EDA software have also been proposed including the graphical control block design in a single design window and the design space exploration method for logic synthesis.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129096133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A tool for low-power synthesis of FSMs with mixed synchronous/asynchronous state memory 具有混合同步/异步状态存储器的fsm低功耗合成工具
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423857
Cao Can, M. O’nils, B. Oelmann
{"title":"A tool for low-power synthesis of FSMs with mixed synchronous/asynchronous state memory","authors":"Cao Can, M. O’nils, B. Oelmann","doi":"10.1109/NORCHP.2004.1423857","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423857","url":null,"abstract":"An efficient way to obtain Finite-State Machines (FSM) with low power consumption is to partition the machine into two or more sub-FSMs and use dynamic power management, where all sub-FSMs not active are shut down, to reduce dynamic power dissipation. In this paper we focus on FSM partitioning algorithms and RT-level power estimation functions that are the key issues in the design of a CAD tool for synthesis of low-power partitioned FSMs. We large! an implementation architecture that is based on both synchronous and asynchronous state memory elements that enables larger power reductions than fully synchronous architectures do. Power reductions of up to 77% have been achieved at a cost of an increase in area of 18%.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128075928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A SW-HW implementation of arbitration protocols 仲裁协议的SW-HW实现
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423867
S. Ramo, T. Seceleanu
{"title":"A SW-HW implementation of arbitration protocols","authors":"S. Ramo, T. Seceleanu","doi":"10.1109/NORCHP.2004.1423867","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423867","url":null,"abstract":"In this study, we discuss arbitration aspects concerning a segmented bus platform for SOC, and analyze a software implementation of the related procedures. Placed somewhere mid-way between the classical system bus and the network on chip approaches, the segmented bus architecture provides certain performance improvements in comparison with the first, while employing a much simpler communication structure and algorithm than those thought for the second. Our implementation strategy targets an FPGA technology.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131928605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Communication scheme for an advanced java co-processor 一种高级java协处理器的通信方案
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423865
T. Säntti, Juha Plosila
{"title":"Communication scheme for an advanced java co-processor","authors":"T. Säntti, Juha Plosila","doi":"10.1109/NORCHP.2004.1423865","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423865","url":null,"abstract":"This paper describes interface strategies for a Java co-processor (from now on JPU). The interface units are inter­ changeable, and share a common communication scheme towards the co-processor. The rst version of the interface is designed for single CPU and single co-processor environment. The other is for a network of multiple CPUs and co­ processors. The co-processor does not need to know what kind of environment is is placed in, as all communication goes through the interface unit. This modularity of the de­ sign makes the co-processor more reusable and allows sys­ tem level scalability. This work is a part of a project focusing on design of an advanced Java co-processor for Java intensive SoC applications.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
RF requirements for multi-hop cellular network repeaters 多跳蜂窝网络中继器的射频要求
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423878
R. S. Karlsson, H. Aniktar, T. Larsen, J. Mikkelsen
{"title":"RF requirements for multi-hop cellular network repeaters","authors":"R. S. Karlsson, H. Aniktar, T. Larsen, J. Mikkelsen","doi":"10.1109/NORCHP.2004.1423878","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423878","url":null,"abstract":"Multi-hop cellular networks are currently being explored for use in future generation cellular networks. This paper is a step towards identifying overall system requirements for the radio frequency (RF) part of terminals for such multi-hop cellular networks. Multi-hop cellular network offer tradeoffs between coverage, capacity and power consumption. Multi-hop networks are also expected to place new requirements on the RF parts of the transceivers of both repeating and mobile devices. In this pope< a set of system requirements are derived for multi-hop enabled RF front-ends. For this purpose, the uplink transmit power distributions and the uplink outage performance for multi-hop networks are investigated. According to simulation results, some RF requirements have been identi ed in both transmitter and receiver sections.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115668864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A single chip 802.11 a/b/g WLAN transceiver 单片802.11 A /b/g WLAN收发器
Proceedings Norchip Conference, 2004. Pub Date : 2004-11-08 DOI: 10.1109/NORCHP.2004.1423866
F. Jonsson, Rami, Adem, James Wilson, Kishore Rama, I. Hyyrylainen, A. Brolin, T. Hakala, Friman, T. Makiniemi, Hanzel, M. Sandén, D. Wallner, Yuxin Guo, T. Lagerstam, L. Noguer, T. Knuuttila, Peter Olofsson, M. Ismai
{"title":"A single chip 802.11 a/b/g WLAN transceiver","authors":"F. Jonsson, Rami, Adem, James Wilson, Kishore Rama, I. Hyyrylainen, A. Brolin, T. Hakala, Friman, T. Makiniemi, Hanzel, M. Sandén, D. Wallner, Yuxin Guo, T. Lagerstam, L. Noguer, T. Knuuttila, Peter Olofsson, M. Ismai","doi":"10.1109/NORCHP.2004.1423866","DOIUrl":"https://doi.org/10.1109/NORCHP.2004.1423866","url":null,"abstract":"A dual-band triple mode radio compliant with the IEEE 802.11 a/b/g standard implemented in a 0.18 μm CMOS process b presented. The transceiver is compatible with a large number of basebands due to its flexible interface towards AD / DA converters and on-chip automatic calibration of-on-chip filters and oscillators. The transceiver achieves a receiver noise figure of 4.9/5.MB for the 2.4GHz/5GHz bands, respectively, and a minimum transmit error vector magnitude (EVM) of 2.5% for both bands. A quadrature accuracy of 0.3° in phase and 0.05dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a better than -34dBc total integrated phase noise. The chip passes ± human body model ESD testing on all pins, including the RF pins. The total die area is 12mm2. The power consumption is 207mW in the receive mode and 247mW in the transmit made using a 1.8Vsupply.","PeriodicalId":208182,"journal":{"name":"Proceedings Norchip Conference, 2004.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128323046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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