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Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems最新文献

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A study on a high-speed Gaussian random number generator 高速高斯随机数发生器的研究
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569211
Byungyang Ahn
{"title":"A study on a high-speed Gaussian random number generator","authors":"Byungyang Ahn","doi":"10.1109/APCAS.1996.569211","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569211","url":null,"abstract":"Gaussian random number generators are employed to simulate the fading phenomena and additive white Gaussian noise of the radio channel. High speed Gaussian random number generators are most important components for the real-time channel simulation of the CDMA systems, because of channel's wideband nature. In this paper we suggest a Gaussian random number generation method, based on central limit theorem with the simple probability density conversion before addition. Using this technique, we can omit some of the input random numbers and adders, which are relatively complex components in the hardware logic of the random number generator.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"52 1","pages":"30-32"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81272128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC 用于流水线ADC的3 v, 1.47 mw, 120 mhz比较器
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569303
J. Ho, H. Cam Luong
{"title":"A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC","authors":"J. Ho, H. Cam Luong","doi":"10.1109/APCAS.1996.569303","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569303","url":null,"abstract":"A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"58 1","pages":"413-416"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89560852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Interconnect simulation based on passivity and method of characteristics 基于无源性和特性方法的互联仿真
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569311
E. Kuh, J. Mao, M.L. Wang
{"title":"Interconnect simulation based on passivity and method of characteristics","authors":"E. Kuh, J. Mao, M.L. Wang","doi":"10.1109/APCAS.1996.569311","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569311","url":null,"abstract":"Interconnect analysis modeling, and simulation will play a major role in the future design of submicron IC and electronic packaging. Existing simulation methods by and large depend on convolution and the well-known Pade approximation of transcendental functions which characterize transmission lines. Unfortunately, Pade approximation does not guarantee stability. In this paper two methods are presented. One is based on using the concept of passivity, and the other uses the traditional method of characteristics. Preliminary results obtained on simple examples are very encouraging.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"42 1","pages":"449-457"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77684331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Accurate logic-level power simulation using glitch filtering and estimation 精确的逻辑级功率仿真使用故障滤波和估计
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569279
W. Tsai, C. Shung, D.C. Wang
{"title":"Accurate logic-level power simulation using glitch filtering and estimation","authors":"W. Tsai, C. Shung, D.C. Wang","doi":"10.1109/APCAS.1996.569279","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569279","url":null,"abstract":"A power estimation tool is required to be faster and more accurate when the power consumption is the chief concern during chip design. A logic-level simulator is a good choice for estimating the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use the logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and the time interval of two consecutive transitions to decide whether these transitions are partial glitches or full transitions. We estimate the transition power of each transition event and summed them. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"57 1","pages":"314-317"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91508005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Low bit-rate image coding for facial movement 面部运动的低比特率图像编码
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569205
K. Takaya, R. T. Reinhardt
{"title":"Low bit-rate image coding for facial movement","authors":"K. Takaya, R. T. Reinhardt","doi":"10.1109/APCAS.1996.569205","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569205","url":null,"abstract":"Low bit-rate facial image coding for intended applications to video telephone is presented. The basic principle for this facial image coding is to use 2D image warping techniques in generating successive video frames from a stored master image. Setting global and local grids, the use of attractant/repellant masses, and bilinear mapping for painting a picture are described along with the necessary image analysis for parameter extraction.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"37 1","pages":"6-9"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90320874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The latest FTTH technologies for full service access networks 全业务接入网的最新FTTH技术
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569268
I. Yamashita
{"title":"The latest FTTH technologies for full service access networks","authors":"I. Yamashita","doi":"10.1109/APCAS.1996.569268","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569268","url":null,"abstract":"Current strong demands on computer communication services like internet access services require economical solutions to provide broadband capabilities to access networks. Several approaches to broaden the so-called access bottleneck have been proposed and tested, that is, HFC using cable modems, metallic cables using ADSL, wireless access, FTTC using VDSL and FTTH. In this paper, the latest technologies to realize economically feasible FTTH systems are presented. The requirements and system technologies to provide various multimedia services as well as conventional telephone services are shown. Various approaches to reduce the access network cost are introduced from system and component technologies point of views. Three types of FTTH systems, Narrowband FTTH, Video Distribution FTTH and High Speed FTTH based on ATM techniques are presented. The international collaboration on full service access networks is discussed. Finally, the field trials of FTTH in Japan are illustrated.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"58 1","pages":"263-268"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91007215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Simulation of reticle seekers using the generated thermal images 利用生成的热图像对定向导引头进行仿真
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569249
H. Hong, Sung-Hyun Han, G. Hong, Jongsoo Choi
{"title":"Simulation of reticle seekers using the generated thermal images","authors":"H. Hong, Sung-Hyun Han, G. Hong, Jongsoo Choi","doi":"10.1109/APCAS.1996.569249","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569249","url":null,"abstract":"This paper presents an efficient simulation method that generates thermal images and gives tracking results of infra-red (IR) reticle seekers. We first construct an IR model of the target having an internal heat source, and generate thermal images produced by the optical system of the reticle seeker and atmospheric turbulence. Using the generated thermal images, we can simulate IR seekers in various cases including countermeasures such as flares. Simulation results show that our method generates accurate images and the constructed loop is applicable to the study of the development of counter-countermeasures.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"4 1","pages":"183-186"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88472033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices 用于高速光通信器件的倒装片键合技术的铅/铟焊料凸点形成
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569305
Haksoo Han, Hyunsoo Chung, Sungkook Park, Y. Joe, Sungsoon Park, Gwanchong Joo, N. Hwang, H. Lee, Kang Seungoo, Song Min-Kyu
{"title":"Pb/In solder bump formation for a flip-chip bonding technique at high speed optical communication devices","authors":"Haksoo Han, Hyunsoo Chung, Sungkook Park, Y. Joe, Sungsoon Park, Gwanchong Joo, N. Hwang, H. Lee, Kang Seungoo, Song Min-Kyu","doi":"10.1109/APCAS.1996.569305","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569305","url":null,"abstract":"The increasing speed of advanced chip technologies has greatly challenged the interconnection methods and processes in order to achieve enhanced capability. We have successfully fabricated the solder bump and it's reflowing process for flip-chip bonding interconnection technique instead of conventional wire bonding for high speed devices. The lead (Pb: 350/spl deg/C) and the Indium (In: 157/spl deg/C) were used for solder bump and deposited by using thermal evaporation. The thickness of the deposited metal for solder bump was in the range of 5/spl sim/6 /spl mu/m thickness. Specially, to increase the accuracy and the reliability of the flip-chip bonding Technique, 3 layer thick photoresist about 30 /spl mu/m was used to control the deposition area for solder bump. It was also used for the lift-off process of excess deposited metal for solder bump. The height of solder bump through the reflowing process was controlled in the range of 10/spl sim/40 /spl mu/m according to the deposited area and shape. Also, the deposited area and shape was one of the most important parameters for solder bump fabrication. In addition, it was found that an oxidized surface layer effects on the increased melting temperature of deposited metal for solder bump. In this process, the reflowing temperature of PB/In (60:40 wt%) solder bumps was 230/spl plusmn/5/spl deg/C.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"421-424"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88636974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-performance VLSI architecture for three-dimensional instrumentation based on a new concurrent memory-access scheme 基于一种新的并发存储器访问方案的三维仪器高性能VLSI体系结构
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569323
S. Lee, M. Hariyama, M. Kameyama
{"title":"High-performance VLSI architecture for three-dimensional instrumentation based on a new concurrent memory-access scheme","authors":"S. Lee, M. Hariyama, M. Kameyama","doi":"10.1109/APCAS.1996.569323","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569323","url":null,"abstract":"A high-performance VLSI architecture for 3-D instrumentation has been proposed based on a new concurrent memory access scheme. The key concept of this architecture is to reduce the number of pixel values to be retrieved and the time required in retrieving pixel values. Accordingly, the time required for the calculation of the mean-absolute difference (MAD) function is reduced and operations that involve memory access are calculated in parallel by a 2-D PE array in the MAD calculation unit (MADU).","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"96 1","pages":"500-503"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88068318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of uncovered region prediction for very low bit rate video coding 无覆盖区域预测在极低码率视频编码中的应用
Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI: 10.1109/APCAS.1996.569237
Yeong-An Jeong, Dong-Wook Kim, Sung-Hyun Han, Jongsoo Choi
{"title":"Application of uncovered region prediction for very low bit rate video coding","authors":"Yeong-An Jeong, Dong-Wook Kim, Sung-Hyun Han, Jongsoo Choi","doi":"10.1109/APCAS.1996.569237","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569237","url":null,"abstract":"This paper presents a new method which generates the uncovered region memory using motion estimation and shows the application of this algorithm for very low bit rate video coding in order to solve the problems of uncovered background region due to the region-based backward motion estimation. The proposed algorithm can be briefly described as this; it detects the changed region by using the information of FD (frame difference) and segmentation, and then as for only this region the backward motion estimation without transmission of shape information is carried out. Therefore, from only motion information the uncovered region background region memory is generated and updated. The contents stored in the uncovered background region memory are referred to whenever the uncovered region comes into existence. The regions with large prediction error are transformed and coded by using DCT. As a result of simulation, the proposed algorithm shows a superior improvement in the subjective and objective image quality as well as a remarkable reduction of transmission error bits.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"28 6","pages":"133-136"},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91493649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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