C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim
{"title":"155M物理层专用集成电路用于ATM网络节点接口的实现","authors":"C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim","doi":"10.1109/APCAS.1996.569213","DOIUrl":null,"url":null,"abstract":"This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An implementation of the 155M physical layer ASIC for ATM network-node interface\",\"authors\":\"C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim\",\"doi\":\"10.1109/APCAS.1996.569213\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569213\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569213","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An implementation of the 155M physical layer ASIC for ATM network-node interface
This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
