155M物理层专用集成电路用于ATM网络节点接口的实现

C. Suh, Sung-Do Kim, H. Jung, Sang-Hoon Choi, Gui Dong Kim, W. Song, Kyung-Soo Kim
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引用次数: 0

摘要

本文介绍了一种用于ATM网络节点接口的155M物理层专用集成电路的实现,该集成电路包括发送合成器、接收位同步器、传输收敛器、微处理器接口和ATM物理接口通用测试与操作UTOPIA。该ASIC完全符合ITU-T和ATM论坛的建议。该芯片采用0.8 /spl mu/m双金属n阱CMOS工艺实现。在9mm /spl times/9.2 mm硅芯片上集成了320,960个晶体管,在5v时使用155 MHz时钟,最大功耗为1.02 W。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An implementation of the 155M physical layer ASIC for ATM network-node interface
This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.
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