An implementation of the 155M physical layer ASIC for ATM network-node interface

Abstract

This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 /spl mu/m double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm/spl times/9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock.