Accurate logic-level power simulation using glitch filtering and estimation

Abstract

A power estimation tool is required to be faster and more accurate when the power consumption is the chief concern during chip design. A logic-level simulator is a good choice for estimating the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use the logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and the time interval of two consecutive transitions to decide whether these transitions are partial glitches or full transitions. We estimate the transition power of each transition event and summed them. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.