{"title":"用于流水线ADC的3 v, 1.47 mw, 120 mhz比较器","authors":"J. Ho, H. Cam Luong","doi":"10.1109/APCAS.1996.569303","DOIUrl":null,"url":null,"abstract":"A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC\",\"authors\":\"J. Ho, H. Cam Luong\",\"doi\":\"10.1109/APCAS.1996.569303\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569303\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569303","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC
A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 /spl mu/m technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at v/sub i+/, DC at v/sub i-/, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed.
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