具有高效布局的容错网格

Toshinori Yamada, S. Ueno
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引用次数: 3

摘要

本文提出了一种实用的网格并行机容错体系结构,该结构适用于只有一个备用处理器,每处理器只有6条通信链路,同时允许一个处理器故障和一个通信链路故障,或两个通信链路故障。我们还表明,这里提出的架构可以有效地布置在线形区域,导线长度最多为6。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fault-tolerant meshes with efficient layouts
This paper presents a practical fault-tolerant architecture for mesh parallel machines that has only one spare processor and has only six communication links per processor while tolerating one processor fault and one communication link fault, or two communication link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most six.
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