2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)最新文献_第9页

A novel contact field plate application in drain-extended-MOSFET transistors 一种新型接触场极板在漏极扩展mosfet晶体管中的应用

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988957

Lin Wei, Cheng Chao, U. Singh, Ruchil Jain, Li Leng Goh, P. R. Verma

引用次数: 6

A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage 一种低导通电压自调节电导率调制soi - light复合结构

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988899

Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su

{"title":"A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage","authors":"Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su","doi":"10.23919/ISPSD.2017.7988899","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988899","url":null,"abstract":"A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ emitter of the NLT structure while the p+ region in the emitter side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at JA=150A/cm2.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Conductivity modulation in the channel inversion layer of very narrow mesa IGBT 极窄台面IGBT通道反转层的电导率调制

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988893

Masahiro Tanaka, A. Nakagawa

引用次数: 14

A novel Injection Enhanced Floating Emitter (IEFE) IGBT structure improving the ruggedness against short-circuit and thermal destruction 一种新型的注入增强浮动发射极(IEFE) IGBT结构，提高了抗短路和热破坏的坚固性

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988939

Riteshkumar Bhojani, J. Lutz, R. Baburske, H. Schulze, F.-J. Niedemostheide

引用次数: 5

A new ESD self-protection structure for 700V high side gate drive IC 一种用于700V高边极驱动集成电路的新型ESD自保护结构

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988880

Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku

引用次数: 10

Evaluation of drain current decrease by AC gate bias stress in commercially available SiC MOSFETs 市售碳化硅mosfet中交流栅极偏置应力降低漏极电流的评估

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988987

M. Sometani, Y. Iwahashi, M. Okamoto, S. Harada, Y. Yonezawa, H. Okumura, H. Yano

引用次数: 2

Current distribution based power module screening by new normal/abnormal classification method with image processing 基于电流分布的电源模块正常/异常分类新方法与图像处理

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988970

M. Tsukuda, Daisuke Yuki, H. Tomonaga, Hyoungseop Kim, I. Omura

引用次数: 0

Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region 具有优化结场效应晶体管区域的13kv SiC mosfet低导通和快速开关

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988982

H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai

{"title":"Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region","authors":"H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai","doi":"10.23919/ISPSD.2017.7988982","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988982","url":null,"abstract":"In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R<inf>onA</inf>) was estimated to be 169 mΩ·cm<sup>2</sup>. The blocking voltage (BV<inf>DSS</inf>) of 13.1 kV was obtained at 10 μA/cm<sup>2</sup>. Owing to a low electric field in the gate oxide (E<inf>ox</inf>), a threshold voltage (V<inf>th</inf>) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Investigation of a latch-up immune silicon controlled rectifier for robust ESD application 用于稳健ESD应用的锁存免疫可控硅整流器的研究

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988949

Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang

{"title":"Investigation of a latch-up immune silicon controlled rectifier for robust ESD application","authors":"Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988949","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988949","url":null,"abstract":"A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I<inf>esd</inf>) path to improve the holding voltage (V<inf>h</inf>) and failure current (I<inf>t2</inf>). The relation between V<inf>h</inf> and base-concentration (N<inf>b</inf>) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V<inf>h</inf> by changing N<inf>b</inf>. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I<inf>ESD</inf> distribution and V<inf>h</inf>. The longer ESD current path improves the V<inf>h</inf> by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I<inf>t2</inf>. DC and dynamic TLP simulation results show the V<inf>h</inf> = 5.3 V of proposed SCR is achieved with a higher failure current (I<inf>t2</inf>) of 1.68e-2A/μm.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125253698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Simple and efficient approach to improve hot carrier immunity of a p-LDMOSFET 一种简单有效的提高p-LDMOSFET热载流子抗扰度的方法

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI: 10.23919/ISPSD.2017.7988955

A. Sakai, K. Eikyu, H. Fujii, T. Mori, Y. Akiyama, Y. Yamaguchi

引用次数: 3