Investigation of a latch-up immune silicon controlled rectifier for robust ESD application

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD) Pub Date : 2017-05-01 DOI:10.23919/ISPSD.2017.7988949

Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang

{"title":"Investigation of a latch-up immune silicon controlled rectifier for robust ESD application","authors":"Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988949","DOIUrl":null,"url":null,"abstract":"A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I<inf>esd</inf>) path to improve the holding voltage (V<inf>h</inf>) and failure current (I<inf>t2</inf>). The relation between V<inf>h</inf> and base-concentration (N<inf>b</inf>) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V<inf>h</inf> by changing N<inf>b</inf>. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I<inf>ESD</inf> distribution and V<inf>h</inf>. The longer ESD current path improves the V<inf>h</inf> by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I<inf>t2</inf>. DC and dynamic TLP simulation results show the V<inf>h</inf> = 5.3 V of proposed SCR is achieved with a higher failure current (I<inf>t2</inf>) of 1.68e-2A/μm.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISPSD.2017.7988949","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

Abstract

A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (Iesd) path to improve the holding voltage (Vh) and failure current (It2). The relation between Vh and base-concentration (Nb) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing Vh by changing Nb. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the IESD distribution and Vh. The longer ESD current path improves the Vh by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the It2. DC and dynamic TLP simulation results show the Vh = 5.3 V of proposed SCR is achieved with a higher failure current (It2) of 1.68e-2A/μm.

查看原文本刊更多论文

用于稳健ESD应用的锁存免疫可控硅整流器的研究

提出了一种具有N+顶层和附加Nwell区(Nwell2)的锁存免疫鲁棒可控硅结构。N+顶层和Nwell2将原有的可控硅划分为三个具有共享发射极的新可控硅，提供更深的ESD电流(Iesd)路径，以提高保持电压(Vh)和失效电流(It2)。给出了LVTSCR中Vh与碱基浓度(Nb)之间的关系，为通过改变Nb来增强Vh的机理提供了深入的见解。顶层N+和NWELL2形成3个不同浓度的碱基区(B1、B2和B3)，优化了IESD分布和Vh。更长的ESD电流路径通过降低电流增益来提高Vh。较深的电流分布使得总温度由内部晶格而不是表面晶格承受，从而改善了It2。直流和动态TLP仿真结果表明，该晶闸管在1.68e-2A/μm的高失效电流(It2)下实现了Vh = 5.3 V。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)

自引率

0.00%

发文量