Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku
{"title":"一种用于700V高边极驱动集成电路的新型ESD自保护结构","authors":"Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku","doi":"10.23919/ISPSD.2017.7988880","DOIUrl":null,"url":null,"abstract":"A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"647 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A new ESD self-protection structure for 700V high side gate drive IC\",\"authors\":\"Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku\",\"doi\":\"10.23919/ISPSD.2017.7988880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.\",\"PeriodicalId\":202561,\"journal\":{\"name\":\"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)\",\"volume\":\"647 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/ISPSD.2017.7988880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISPSD.2017.7988880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new ESD self-protection structure for 700V high side gate drive IC
A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.