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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)最新文献

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High-speed and low-power real-time programmable video multi-processor for MPEG-2 multimedia chip on 0.6 /spl mu/m TLM CMOS technology 高速低功耗实时可编程视频多处理器为MPEG-2多媒体芯片，采用0.6 /spl μ m TLM CMOS技术
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759995
Seung-Min Lee, Jin-H. Chung, Mike-Myung-Ok Lee
{"title":"High-speed and low-power real-time programmable video multi-processor for MPEG-2 multimedia chip on 0.6 /spl mu/m TLM CMOS technology","authors":"Seung-Min Lee, Jin-H. Chung, Mike-Myung-Ok Lee","doi":"10.1109/ASPDAC.1999.759995","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759995","url":null,"abstract":"We developed a Video Multi Processor (VMP) for image compression and decompression schemes of MPEG (especially MPEG-2) in this study. The VMP would apply to programmable architecture, various flexibilities to implement real-time image compression algorithm, and other many applications such as DVD-CD ROM authoring tool and videophone/teleconferencing systems. IO architecture of the VMP is designed for the multi-processor functionality in which uses many VMPs according to required arithmetic quantities of the system. Further, the architecture of the VMP system is simplified by processing the necessary peripheral IO system operations within the processor.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An integrated battery-hardware model for portable electronics 便携式电子设备的集成电池硬件模型
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759725
Massoud Pedram, C. Tsui, Qing Wu
{"title":"An integrated battery-hardware model for portable electronics","authors":"Massoud Pedram, C. Tsui, Qing Wu","doi":"10.1109/ASPDAC.1999.759725","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759725","url":null,"abstract":"We describe an integrated model of the hardware and the battery sub-systems in battery-powered VLSI systems. We demonstrate that, under this model and for a fixed operating voltage, the battery life decreases super-linearly as the average current dissipation increases. With the aid of analyses and empirical studies, we then show that the implications of this phenomenon are far-reaching and change our perceptions about low power design techniques targeted toward battery-powered VLSI circuits.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127664406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A multi-level FPGA synthesis method supporting HDL debugging for emulation-based designs 一种多级FPGA合成方法，支持基于仿真设计的HDL调试
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760031
Wen-Jong Fang, Peng-Cheng Kao, A. Wu
{"title":"A multi-level FPGA synthesis method supporting HDL debugging for emulation-based designs","authors":"Wen-Jong Fang, Peng-Cheng Kao, A. Wu","doi":"10.1109/ASPDAC.1999.760031","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760031","url":null,"abstract":"Converting an HDL-based design into an emulation system for design verification is an extremely complex and time-consuming task. One possible solution to improve productivity is an effective emulation-based design methodology that exploits the modularity of designs. This paper develops and explores such a methodology. We present a multi-level synthesis method which is able to establish a direct link between High-level Descriptive Language (HDL) constructs and corresponding circuit designs. This feature greatly facilitates HDL debugging capabilities such that when bugs are detected in sub-netlists, links allow the corresponding HDL source code to be easily recognized. This powerful feature greatly reduces design debugging time. Experimental results on a set of industrial designs are reported in order to demonstrate the effectiveness of the proposed synthesis methodology.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Diagnosing single faults for interconnects in SRAM based FPGAs 基于SRAM的fpga互连单故障诊断
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760014
Yinlei Yu, Jian Xu, Wei-Kang Huang, F. Lombardi
{"title":"Diagnosing single faults for interconnects in SRAM based FPGAs","authors":"Yinlei Yu, Jian Xu, Wei-Kang Huang, F. Lombardi","doi":"10.1109/ASPDAC.1999.760014","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760014","url":null,"abstract":"This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used. For non-adaptive test, eight programming steps is required to diagnose all the possible faults under the given single fault model. The accuracy of the fault diagnosing is one segment for a segment stuck-at or stuck-open fault, a segment pair for a bridge fault, a switch for switch stuck-on or stuck-off fault.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133801177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An on-chip automatic tuning circuit using integration level approximation technique 一种采用积分级逼近技术的片上自动调谐电路
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760010
Lee Sung-Dae, Jang Myung-Jun, Lee Won-Hyo
{"title":"An on-chip automatic tuning circuit using integration level approximation technique","authors":"Lee Sung-Dae, Jang Myung-Jun, Lee Won-Hyo","doi":"10.1109/ASPDAC.1999.760010","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760010","url":null,"abstract":"An on-chip automatic tuning circuit with proposed integration level approximation technique was designed in a 0.65 m 3.3 V CMOS process for tuning of the variation passive component. To verify the tuning efficiency of the proposed circuit, three types of 2nd-order biquad RC active filters were used. The cut-off frequency (f/sub c/) error of filter with the proposed tuning circuit can be reduced by a new algorithm that considers the variation of capacitor value in capacitor arrays as well as the variation of normal component. This circuit runs so fast that it can also be applied to real-time calibration. This tuning circuit with 4-bits resolution achieves -1.6%/spl sim/+1.5% cut-off-frequency error for /spl plusmn/56% RC variation.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"37 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114021025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysing forced oscillators with multiple time scales 多时间尺度强迫振子分析
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759709
O. Narayan, J. Roychowdhury
{"title":"Analysing forced oscillators with multiple time scales","authors":"O. Narayan, J. Roychowdhury","doi":"10.1109/ASPDAC.1999.759709","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759709","url":null,"abstract":"We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formulation that captures complex dynamics in autonomous nonlinear systems of arbitrary size or complexity. We present computationally efficient numerical methods for solving large practical problems using the WaMPDE. Our approach explicitly calculates a time-varying local frequency that matches intuitive expectations. Applications to voltage-controlled oscillators demonstrate speedups of two orders of magnitude.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121969222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
16-bit DSP and system for baseband/voiceband processing of IS-136 cellular telephony 用于IS-136蜂窝电话基带/语音带处理的16位DSP及系统
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759707
Tae Hun Kim, Jeongsik Yang, Kyoohyun Lim, Jin Wook Kim, Jeong Eun Lee, H. Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim
{"title":"16-bit DSP and system for baseband/voiceband processing of IS-136 cellular telephony","authors":"Tae Hun Kim, Jeongsik Yang, Kyoohyun Lim, Jin Wook Kim, Jeong Eun Lee, H. Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim","doi":"10.1109/ASPDAC.1999.759707","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759707","url":null,"abstract":"This paper presents 16-bit DSP processor and system for baseband and voiceband processing of IS-136 digital cellular telephony that is North America TDMA standard. The DSP, named MIGHTI, that is designed for mobile communication applications, has some special instructions that allow instruction pipelining for the compound operations. MIGHTI includes a low-power 16 K-word flexible port fullcustom memory. With MIGHTI, IS-136 baseband and voiceband processing that normally requires 45 MIPS in a conventional DSP, is performed in just 36 MIPS. The system developed for baseband and voiceband processing does meet the requirements of the IS-136 standard.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127850039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Benchmark circuits improve the quality of a standard cell library 基准电路提高了标准单元库的质量
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759988
Rung-Bin Lin, I. S. Chou, Chi-Ming Tsai
{"title":"Benchmark circuits improve the quality of a standard cell library","authors":"Rung-Bin Lin, I. S. Chou, Chi-Ming Tsai","doi":"10.1109/ASPDAC.1999.759988","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759988","url":null,"abstract":"The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment. Two releases of a 0.25 /spl mu/m standard cell library have been tested by these two benchmark circuits to ensure their quality.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130391816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Watermarking layout topologies 水印布局拓扑
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.759998
E. Charbon, I. Torunoglu
{"title":"Watermarking layout topologies","authors":"E. Charbon, I. Torunoglu","doi":"10.1109/ASPDAC.1999.759998","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.759998","url":null,"abstract":"Watermarking is a technique currently being developed to effectively protect intellectual property of various types. In this paper a formalization of the watermarking problem is presented in the context of IC physical design. A class of algorithms is proposed for implanting arbitrary codes in the inherent structure of layout topologies. Similarly, a method is given to reconstruct the original watermark for a given design. The concepts of robustness against forgery and theft tracking are analyzed in light of the proposed algorithms. Examples show the suitability of the approach.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130739131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
New multilevel and hierarchical algorithms for layout density control 新的多层分层布局密度控制算法
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI: 10.1109/ASPDAC.1999.760000
A. Kahng, G. Robins, Anish Singh, A. Zelikovsky
{"title":"New multilevel and hierarchical algorithms for layout density control","authors":"A. Kahng, G. Robins, Anish Singh, A. Zelikovsky","doi":"10.1109/ASPDAC.1999.760000","DOIUrl":"https://doi.org/10.1109/ASPDAC.1999.760000","url":null,"abstract":"Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing (CIMP) which has varying effects on device and interconnect features, depending on local layout characteristics. To reduce manufacturing variation due to CMP and to improve yield and performance predictability, the layout needs to be made uniform with respect to certain density criteria, by inserting \"fill\" geometries into the layout. This paper presents an efficient multilevel approach to density analysis that affords user-tunable accuracy. We also develop exact fill synthesis solutions based on combining multilevel analysis with a linear programming approach. Our methods apply to both flat and hierarchical designs.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129628665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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