International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)最新文献

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Laser-assisted bump transfer for flip chip assembly 用于倒装芯片组装的激光辅助凹凸转移
C.H. Wang, A. Holmes, S. Gao
{"title":"Laser-assisted bump transfer for flip chip assembly","authors":"C.H. Wang, A. Holmes, S. Gao","doi":"10.1109/EMAP.2000.904137","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904137","url":null,"abstract":"This paper describes a novel laser-assisted bumping technique for flip chip assembly. Copper bumps, with gold bonding layers and intermediate nickel barriers, are fabricated by UV lithography and electroplating on quartz wafers with pre-deposited polyimide layers. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using laser light incident through the carrier. Bump fabrication, parallel bonding, and chip release have been successfully demonstrated for test chips having 28 peripheral I/Os on 127 /spl mu/m pitch. Visual inspection of bump cross-sections and individual bump shear test measurements have been carried out for chips bumped by the new method.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Thermal/mechanical analysis of novel C-TSOP using nonlinear FEM method 基于非线性有限元法的新型C-TSOP热/力学分析
Ji-Cheng Lin, K. Chiang
{"title":"Thermal/mechanical analysis of novel C-TSOP using nonlinear FEM method","authors":"Ji-Cheng Lin, K. Chiang","doi":"10.1109/EMAP.2000.904182","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904182","url":null,"abstract":"This paper describes a novel ceramic thin-small-outline package (C-TSOP) to meet the thermal performance and long-term reliability considerations of low-pin-count and high-performance electronic devices, especially for memory devices. To improve the disadvantages of molding compounds and simplify the fabrication process, the molding compound is replaced by a ceramic-like stiffener which is adhered to the leadframe by tape or adhesive. The ceramic-like stiffener would overcome the low thermal conductivity problem of molding compound in a conventional lead-on-chip TSOP (LOC-TSOP) and increase the thermal dissipation efficiency. In this paper, 3D nonlinear finite element models of both the conventional and novel LOC-TSOPs have been established. Various heat generation scenarios are applied to the 3D nonlinear models under natural convection conditions for evaluation of heat dissipation capability and thermal resistance of the packages. Moreover, the material properties and solder joint reliability of the packages are also investigated. In order to compare solder joint reliabilities of the novel and conventional LOC-TSOPs, a nonlinear finite element method is used to analyze the physical behaviors of packages under thermal loading conditions. The thermal fatigue life of the solder joints has been estimated in terms of equivalent plastic strain. The results are compared to the experiments in the literature in order to verify the accuracy of the finite element models. From the results, it can be concluded that the novel C-TSOP package implies excellent thermal performance and solder joint reliability.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115212930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Observations of solder paste reflow by means of electrical measurements 用电测量法观察锡膏回流
S. Mannan, D. Hutt, D. Whalley, P. Conway
{"title":"Observations of solder paste reflow by means of electrical measurements","authors":"S. Mannan, D. Hutt, D. Whalley, P. Conway","doi":"10.1109/EMAP.2000.904149","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904149","url":null,"abstract":"This paper presents a method for exploring the changes occurring at the surfaces of solder particles during the reflow soldering process. The method involves measuring changes in electrical resistance of a sample of paste as a function of test voltage. The results are used to estimate the size and nature of electrical contact spots between the particles, and how these depend on temperature and time. The activation energy of the process responsible for increasing the size of contact spots is deduced for RA and RMA type fluxes and it is shown that sintering is not the dominant mechanism for increasing contact size. These results, together with a programme of CFD studies are expected to help improve solder paste formulations.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126143071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New anisotropic conductive adhesives for low cost and reliable flip chip on organic substrates applications 新型各向异性导电胶粘剂用于低成本和可靠的有机基板倒装芯片应用
K. Paik, M. Yim
{"title":"New anisotropic conductive adhesives for low cost and reliable flip chip on organic substrates applications","authors":"K. Paik, M. Yim","doi":"10.1109/EMAP.2000.904168","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904168","url":null,"abstract":"Flip chip assembly on organic substrates using ACAs (anisotropic conductive adhesives) has advantages such as easier processing, good electrical performance, lower cost, green processes, and organic substrate-compatible low temperature processing. ACAs are composed of epoxy polymer resin and conductive fillers (less than 10 wt.%). ACAs thus have almost the same CTE values as epoxy alone, which are higher than conventional underfill materials with silica fillers. It is thus necessary to lower the ACA CTE value for more reliable flip chip assembly on organic substrates. New ACA composites with conductive and nonconductive fillers were devised. In this paper, we studied the effect of fillers on the thermo-mechanical properties of modified ACA composites and the reliability of flip chip assembly on organic substrates using modified ACAs and electroless Ni and Au stud bumps. As nonconducting filler content increased, CTE values decreased and storage modulus at room temperature increased. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity/temperature, and high temperature/dry test. It was noted that lowering ACA CTEs greatly enhanced thermal cycling reliability. Results also showed that flip chip assembly using modified ACAs with lower CTEs and higher modulus exhibited slightly better contact resistance behavior than conventional ACAs without nonconducting fillers. The greater reliability of flip chip on organic substrates using the new ACAs can lead to new low cost flip chip on organic substrate applications such as smart cards, RF, memory devices, etc.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A method to quantify the surface insulation resistance performance of conformal coatings exposed to different temperature/humidity conditions 一种量化不同温度/湿度条件下适形涂层表面绝缘电阻性能的方法
P. Tomlins
{"title":"A method to quantify the surface insulation resistance performance of conformal coatings exposed to different temperature/humidity conditions","authors":"P. Tomlins","doi":"10.1109/EMAP.2000.904178","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904178","url":null,"abstract":"Typical conformal coatings based on different chemistries and formulated by different manufacturers are selected for a particular application on the basis of a single value for surface insulation resistance measured at a particular temperature and humidity. This information is limited in that the performance of the coating under a wider range of environmental conditions as might be encountered during the product lifetime cannot be assessed. This procedure describes a method for determining two indices that can be used to quantify the performance of conformal coatings over a range of temperatures under damp conditions.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130679566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new method using energy release elements for evaluating bonding strength [packaging] 一种利用能量释放元素评估结合强度的新方法[包装]
T. Hatsuda, R. Minamitani
{"title":"A new method using energy release elements for evaluating bonding strength [packaging]","authors":"T. Hatsuda, R. Minamitani","doi":"10.1109/EMAP.2000.904164","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904164","url":null,"abstract":"We have developed a new method, based on the concept of energy release rate, for evaluating bonding strength. This method uses a finite element approach and places \"energy release elements (EREs)\" (which mathematically represent the energy release due to debonding) between the interface of two materials. The characteristic of EREs is represented by the stress-elongation relationship of the elements. This relation is defined by two parameters: maximum stress and elongation before fracture. The two parameters are determined by two measurements. By using this method, we estimated the bonding strength of photoresist patterns on Cu substrates and the debonding temperature of joints made from resin and steel. The estimated values of debonding forces and debonding temperatures closely agree with the measured ones. This close agreement shows that the new method can consistently estimate bonding strength over a wide range of shapes and load conditions.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114074560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Moisture sensor using reactive sputtered TiO/sub 2/ thin film with negative substrate bias 水分传感器采用负衬底偏压反应溅射TiO/sub /薄膜
L. Chow, M. Yuen, P. Chan, A. Teng
{"title":"Moisture sensor using reactive sputtered TiO/sub 2/ thin film with negative substrate bias","authors":"L. Chow, M. Yuen, P. Chan, A. Teng","doi":"10.1109/EMAP.2000.904198","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904198","url":null,"abstract":"Moisture is known as a major factor in degrading the reliability of electronic packages. It is estimated that over 40% of failures in electronic devices are induced by moisture. The use of micro-moisture-sensing-chips in electronic package reliability tests can provide in-situ and real-time monitoring of device failures under controlled environmental conditions. Some previously published fabrication techniques of high performance moisture sensors include a very high temperature powder sintering method (Jain et al, 1999; Katayama et al, 1990; Slunecko et al, 1992), the sol-gel method (Montesperelli et al, 1995) and etching porous silicon (Macko, 1982) under complex and sophisticated process control. All of these methods are incompatible with conventional IC processing. In this paper, simple and low temperature fabricated moisture sensing chips using a reactive sputtering process in thin film technology are characterized. The reactive sputtering process has been widely employed in IC batch production for its high process control and uniformity. The adsorption response, which is well fitted into a Brunauer, Emmett and Teller (BET) type III model, and atomic force microscope (AFM) images illustrate that the sensing films are pore-free. A process window for improving hysteresis performance is obtained by applying a negative substrate bias during sputtering and increasing the annealing time. The sensitivity of four orders of magnitude in DC current change over 11%-97% relative humidity (RH) is achieved.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132979956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low cost flip chip bumping 低成本倒装芯片碰撞
T. Oppert, T. Teutsch, E. Zakel
{"title":"Low cost flip chip bumping","authors":"T. Oppert, T. Teutsch, E. Zakel","doi":"10.1109/EMAP.2000.904135","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904135","url":null,"abstract":"Flip chip (FC) technology is a driving force for increased speed and performance along with higher I/O count, and has therefore a high level of importance for a variety of applications. A breakthrough, however, will be the use of flip chip due to cost reduction. To achieve this aim, it is essential to use low cost bumping techniques. However, to provide FC technologies for devices with high I/O count and high pin density applications like microcontrollers, RAMBUS devices, etc., it is necessary to redistribute the historically peripheral bond pads with ultra fine pad pitch into a wafer level CSP. This paper describes a low cost electroless Ni/Au under bump metallization (UBM), a wafer level redistribution process based on electroless copper circuitization and different methods of single and multiple solder ball placement.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Enhancement of moisture sensitivity performance of a FBGA FBGA湿敏性能的增强
Lee Teck Kheng, Lee Kian Chai, Chai Yih Ming, Ng Yew Hong
{"title":"Enhancement of moisture sensitivity performance of a FBGA","authors":"Lee Teck Kheng, Lee Kian Chai, Chai Yih Ming, Ng Yew Hong","doi":"10.1109/EMAP.2000.904201","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904201","url":null,"abstract":"One of the main package reliability limitations of fine pitch BGA (FBGA) is its moisture sensitivity performance, i.e. popcorn failure. Package reliability of different packaging materials is thus normally employed to determine the optimal material combination for good moisture performance. This paper attempts to understand the impact of solder mask design on the package moisture sensitivity. It also determines the die attach adhesion strength material and mold compound selection criteria. By correlating the shear strength to package moisture sensitivity performance, it provides an approach for selecting die attach materials that will enhance the moisture resistance of the package.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117045828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Study on failure mode of solder bump fabricated using eutectic solder electroplating process 共晶焊料电镀工艺制作凸点失效模式的研究
Guo-Wei Xiao, P. Chan, A. Teng, Jian Cai, M. Yuen
{"title":"Study on failure mode of solder bump fabricated using eutectic solder electroplating process","authors":"Guo-Wei Xiao, P. Chan, A. Teng, Jian Cai, M. Yuen","doi":"10.1109/EMAP.2000.904129","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904129","url":null,"abstract":"The electroplating-based flip chip process has many advantages over other solder bumping methods, where the bump fabrication process can affect the reliability of solder joints. In this paper, the effect of the UBM and electroplating process of the solder bump on the shear strength of the solder bump is studied, as well as the relationship between the shear test failure mode and solder bump fabrication process. It is reported that the Cu surface roughness is affected by the Cu plating current density and the appropriate current density is in a range from 10/spl sim/40 mA/cm/sup 2/. The solder bump plating process temperature should be within 30-35/spl deg/C. It is observed that the growth kinetics of intermetallic compound formation are affected by the Cu stud structure. The ratio of Cu/sub 3/Sn to the total Cu-Sn IMC layer thickness was from 0.5 to 0.15 with various Cu microstructures at 150/spl deg/C during thermal aging tests. The activation energy was in the range of 0.78 eV to 1.14 eV. Five shear test failure modes are analyzed which are related to the electroplating process.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117145320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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