International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)最新文献

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The investigation of some properties of copper alloys for lead frame 引线架用铜合金若干性能的研究
Huang Fuxiang, Huang Le, M. Ju-sheng, W. Qian, Wang Qinglei, Lu Chao
{"title":"The investigation of some properties of copper alloys for lead frame","authors":"Huang Fuxiang, Huang Le, M. Ju-sheng, W. Qian, Wang Qinglei, Lu Chao","doi":"10.1109/EMAP.2000.904186","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904186","url":null,"abstract":"Lead frames are one of the most important component parts of discrete and IC devices. Due to their good electrical conductivity and cost, copper alloys for lead frames are widely used in IC packages. In this paper, some properties of copper alloys for lead frames, such as etching properties, etc, are researched. The results showed that because of the different etching mechanisms and alloy elements added to the copper alloy, the etching rates of copper alloys in low concentration ferric chloride are much higher than those of the same alloys in higher concentrations. The influence of the dimensions of eight different copper alloys to the etching properties are compared. The variety of this factor is displayed in the coordinate system. Copper solderability is also investigated in the paper.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122408260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Investigation of lead cracking in TSSOP during burr-up forming process TSSOP中毛刺成形过程中铅裂纹的研究
E. Chung, T. Xu, Deming Liu
{"title":"Investigation of lead cracking in TSSOP during burr-up forming process","authors":"E. Chung, T. Xu, Deming Liu","doi":"10.1109/EMAP.2000.904190","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904190","url":null,"abstract":"Cracking was encountered on stamped TSSOP leads during a burr-up forming process. Most of the cracks were presented at the corner of the dambar and the external lead on the outer-bending surface. A comprehensive investigation including metallographical examination, material elongation testing and on-site modification testing was conducted to identify the causes of the cracking, and to suggest remedies to reduce or eliminate the problem. Results showed that the leadframe dambar radius, burr height, materials ductility, lead forming methods and forming profile are the factors related to the cracking tendency. Among them, the dambar radius, burr height and forming profile are the three essential factors causing lead cracks for the current burr-up forming process. The leadframe design was then modified by increasing the dambar radius and the forming profile was changed by enlarging the form anvil radius. Such modifications resulted in zero lead cracking with the same leadframe material at the same stamping burr height.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122776997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced substrate technology for ball grid array in electronic packaging 电子封装中球栅阵列的先进衬底技术
Y. Wang, T. Her
{"title":"Advanced substrate technology for ball grid array in electronic packaging","authors":"Y. Wang, T. Her","doi":"10.1109/EMAP.2000.904176","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904176","url":null,"abstract":"Consumer demand for high density multi-function electronics has driven the development of new electronic packaging technologies at chip level and substrate level. However, implementing high density chip level packaging in volume production requires higher density interconnect substrates. Substrate material is a very important part of ball grid arrays (BGA) in electronic packaging. It not only affects the cost of package, but also the reliability and performance. This presentation therefore covers the substrate manufacturing process, comparison of core materials (flex and rigid), and some advanced substrates. Plating is a key factor in the manufacturing process. Some of currently used plating techniques for both copper (Cu) and nickel (Ni)/gold (Au) are introduced. Flex substrate is an emerging substrate material. The advantages and disadvantages are also compared. Some advanced substrates, such as high-density interconnection (HDI), high power solutions, build up substrates and thin/fine pitch substrates, are all presented.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126062025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Under bump metallisation of fine pitch flip-chip using electroless nickel deposition 微距倒装芯片的碰撞金属化化学镀镍
C. Liu, D. Hutt, D. Whalley, P. Conway, S. Mannan
{"title":"Under bump metallisation of fine pitch flip-chip using electroless nickel deposition","authors":"C. Liu, D. Hutt, D. Whalley, P. Conway, S. Mannan","doi":"10.1109/EMAP.2000.904134","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904134","url":null,"abstract":"For solder based flip-chip assembly, under-bump metallisation (UBM) layer deposition on the Al die bondpads is the first step in the wafer bumping process. The UBM is necessary, as the fragile Al pad has a tough oxide layer that cannot be soldered without the use of strong flux and a barrier layer is required to prevent dissolution of the bondpad into the solder during reflow. The UBM requirements are therefore to provide a solder wettable surface and to protect the underlying Al bondpad during and after assembly. In addition, the UBM deposition process itself must remove any oxide layers on the bondpads to ensure a low resistance interface between pad and UBM. This paper reports a study of the electroless nickel deposition process for the UBM of wafers that are subsequently to be bumped using solder paste printing. This work has extended the process from previous trials on 225 /spl mu/m pitch devices to wafers including die with sub-100 /spl mu/m pitch bondpads. The effect of the various pre-treatment etch processes and zincate activation on the quality of the final electroless Ni bump has been investigated. SEM examination of samples at each stage of the bumping process has been used to aid detailed understanding of the activation mechanisms and to determine their effects on the electroless Ni bump morphology. In addition, bump shear testing has been used to determine the best pre-treatment regime to ensure good adhesion of the electroless Ni to the bondpad. Finally, bumped die electrical resistance measurements have been used to confirm that the pre-treatment procedures are producing a low resistance interface between the Al and electroless Ni.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127515387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A design and manufacturing solution for high reliable non-leaded CSP's like QFN 为QFN等高可靠性无铅CSP提供设计和制造解决方案
G. Kuhnlein, A. Bos
{"title":"A design and manufacturing solution for high reliable non-leaded CSP's like QFN","authors":"G. Kuhnlein, A. Bos","doi":"10.1109/EMAP.2000.904173","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904173","url":null,"abstract":"The ongoing miniaturization and increasing functionality of electronic equipment have forced the semiconductor industry to develop smaller and thinner devices in ever-shorter cycles. The trend for chip scale area/perimeter array packages is obvious. One of these extremely miniaturized IC packages, presented by Matsushita under the name QFN, has rapidly become popular. However, one concern is the limited device reliability (JEDEC moisture level 3) which requires improvements for main markets such as telecommunication and automotive electronics. Rapidly implemented miniaturization in the past has led to reduced device reliability, e.g. for the well-known \"popcorn phenomenon\", from which most thin devices like PBGAs, TQFPs, TSOPs, etc., suffer. In addition, increasing time to market pressure forces the industry to shorten package design time. Under this pressure, the complexity and link between package manufacturability and device reliability is sometimes neglected. The resulting dissatisfaction has initiated a design and manufacturing process research program, targeting best board assembly quality and a reliability performance level of at least JEDEC-moisture level 1. By carefully analyzing all constraints which limit device and board assembly quality of such new devices using all past experiences and by considering the capabilities of existing and established assembly and packaging technologies, it should be possible to build and economically manufacture such devices in high volume, achieving the required board assembly quality and device reliability in the requested cost frame.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133967572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of no-flow underfill for lead-free bumped flip-chip assemblies 无铅凸型倒装芯片组件无流底填料的开发
Zhuqing Zhang, C. Wong
{"title":"Development of no-flow underfill for lead-free bumped flip-chip assemblies","authors":"Zhuqing Zhang, C. Wong","doi":"10.1109/EMAP.2000.904170","DOIUrl":"https://doi.org/10.1109/EMAP.2000.904170","url":null,"abstract":"The no-flow underfill process in flip-chip assembly is promising for a smaller, faster and more cost-efficient packaging technology. Currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents a new no-flow underfill for lead-free solder bumped flip-chip assemblies. Many epoxy resin/HMPA/metal acetylacetonate material systems have been screened in terms of their curing kinetics. Some potential base formulations with curing peak temperatures higher than 200/spl deg/C were selected for further study. The proper fluxing agents were developed and the effects of fluxing agents on the curing kinetics and cured material properties of the potential base formulations were studied by differential scanning calorimetry (DSC), thermo-mechanical analyzer (TMA), dynamic-mechanical analyzer (DMA), thermo-gravimetric analyzer (TGA), and rheometer. The results show that the addition of flux significantly reduced the curing temperature and limits the potential of many formulations for application in lead-free bumped flip chip assemblies. The fluxing capability of several no-flow formulations is evaluated using wetting testing of lead-free solder balls on a copper board. The feasibility of the developed no-flow underfill is demonstrated using a lead-free bumped flip-chip package, which shows 100% interconnection yield after solder reflow.","PeriodicalId":201234,"journal":{"name":"International Symposium on Electronic Materials and Packaging (EMAP2000) (Cat. No.00EX458)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130010075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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