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Low power recording and digitizing circuits for neural prosthetics 用于神经修复的低功耗记录和数字化电路
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016168
M. Poustinchi, R. G. Stacey, S. Musallam
{"title":"Low power recording and digitizing circuits for neural prosthetics","authors":"M. Poustinchi, R. G. Stacey, S. Musallam","doi":"10.1109/ICCDCS.2014.7016168","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016168","url":null,"abstract":"Significant progress has been made in the field of neural prosthetics lately. In order to improve and invent novel wearable and implantable devices, low power consumption is one of the most important concerns. This article discusses low power circuits which are designed, fabricated and tested in our lab which are essential building blocks for neural prosthetics. The circuits include a nano-power current conveyor which senses picoscale to microscale current which corresponds to micro molar neurotransmitter concentration; a nano-power neural amplifier for action potential (AP) detection and amplification and a micro-power ΣΔ analog to digital convertor (ADC) to convert the analog signal (AP or neurotransmitter concentration) to digital codes. These circuits are fabricated in CMOS 0.18 μ technology and tested using recorded signals from posterior parietal cortex of a macaque monkey in our lab.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bulk/surface micromachined polymems test chip for the characterization of electrical, mechanical and thermal properties 用于表征电学、机械和热性能的大块/表面微机械聚合物测试芯片
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016162
F. J. Quinones-N, D. Díaza, W. Calleja-A, F. J. De la Hidalga-W, O. Malik, C. Reyes-B, J. Molina-R, M. Moreno-M., C. Zuniga-I, P. Rosales-Q
{"title":"Bulk/surface micromachined polymems test chip for the characterization of electrical, mechanical and thermal properties","authors":"F. J. Quinones-N, D. Díaza, W. Calleja-A, F. J. De la Hidalga-W, O. Malik, C. Reyes-B, J. Molina-R, M. Moreno-M., C. Zuniga-I, P. Rosales-Q","doi":"10.1109/ICCDCS.2014.7016162","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016162","url":null,"abstract":"In this work we present the design and fabrication of a test chip to be used for the characterization of the main electrical, mechanical and thermal properties of the structural materials involved in the development of polysilicon-based electrothermal actuators. With this combined bulk/surface micromachined chip, parameters such as Young's modulus (E), stretching or compression stresses (±σ), stress gradients (± Δε), electrical resistivity (ρe), doping level (n+), thermal conductivity (K), and thermal capacitance (C) can be obtained. This test chip was fabricated using the PolyMEMS-INAOE fabrication process, in which the main materials involved are silicon oxide, silicon nitride, phosphosilicate glass, aluminum, mono- and polycrystalline silicon. In this combined micromachining technology, the polysilicon film is the main structural material and it is used to build the mechanical actuators.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131381119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Short channel continuous model for double-gate junctionless transistors 双栅无结晶体管的短沟道连续模型
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016158
B. Cardoso Paz, M. Pavanello, Fernando Avila, A. Cerdeira
{"title":"Short channel continuous model for double-gate junctionless transistors","authors":"B. Cardoso Paz, M. Pavanello, Fernando Avila, A. Cerdeira","doi":"10.1109/ICCDCS.2014.7016158","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016158","url":null,"abstract":"This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128502134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modelling the memristor at functional level by using homotopy methods 用同伦方法对忆阻器进行功能级建模
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016178
A. Sarmiento-Reyes, L. Hernández Martínez, G. Diaz-Arango, C. G. Martinez Cervantes, R. Rodriguez Solano, H. Vázquez-Leal
{"title":"Modelling the memristor at functional level by using homotopy methods","authors":"A. Sarmiento-Reyes, L. Hernández Martínez, G. Diaz-Arango, C. G. Martinez Cervantes, R. Rodriguez Solano, H. Vázquez-Leal","doi":"10.1109/ICCDCS.2014.7016178","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016178","url":null,"abstract":"The nanometric memristor has emerged as an important device that foresees novel features for analogue and digital systems. As an immediate consequence, there is a strong need for smart models of the memristor that not only handle the Physics of the device but that also result of application for electric circuit simulation. The ultimate goal is to allow the memristor to be incorporated to the design path of hybrid circuits, i.e. circuits that contain traditional devices and memristors. In this work, a memristor model is obtained by solving the differential equation, that governs the physical behaviour, with a special class of homotopy method. The final model is shaped in a closed-form that can be used at functional level for simulation purpouses.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122596479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural network and fuzzy logic in a speed close loop for DTC induction motors 神经网络与模糊逻辑在直接转矩感应电动机转速闭环中的应用
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016166
P. Ponce, A. Molina, A. Téllez
{"title":"Neural network and fuzzy logic in a speed close loop for DTC induction motors","authors":"P. Ponce, A. Molina, A. Téllez","doi":"10.1109/ICCDCS.2014.7016166","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016166","url":null,"abstract":"Direct Torque Control (DTC) is known to produce quick and robust response in AC drives. However, during steady state, torque, flux and current ripple occur. An improvement of the electric drive can be obtained using a DTC scheme based on the Space Vector Modulation (SVM) which reduces the torque and flux ripple. The proposed control scheme considers the rotor resistance variation. This paper also discusses the application of Type-2 Fuzzy speed Control under uncertain stimuli and an Artificial Neural Network (ANN) as a speed estimator. The capability and precision of this scheme as a speed controller and estimator are verified by different conditions and it is concluded that the proposed control scheme produces good results.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126891187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Quasi-optimal values in the Hamiltonian-based synchronization of chaotic systems 混沌系统基于哈密顿同步的拟最优值
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016177
J. Muñoz-Pacheco, L. C. Gómez Pavón, O. Félix-Beltrán, A. Luis-Ramos
{"title":"Quasi-optimal values in the Hamiltonian-based synchronization of chaotic systems","authors":"J. Muñoz-Pacheco, L. C. Gómez Pavón, O. Félix-Beltrán, A. Luis-Ramos","doi":"10.1109/ICCDCS.2014.7016177","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016177","url":null,"abstract":"In this paper a quasi-optimal surface for the observer gain in a Hamiltonian-based controller with applications in chaos synchronization is reported. The synchronization scheme is based on a master-slave topology composed of two chaotic oscillators with identical parameters but by using different initial conditions. Therefore, a trade-off analysis on the synchronization regime and the observer gains (K) in an n-scroll chaotic system is obtained. Lyapunov exponents are not required to prove the stability of the synchronization error, which could expand the study to many others chaotic systems. The synchronization error can be obtained as lower than 0.0001 for certain types of permutations of K. Numerical simulations validate the theoretical background and the usefulness of the proposed approach.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127218202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing high power RF amplifiers: An analytic approach 设计高功率射频放大器:一种分析方法
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016181
M. M. De Souza, M. Rasheduzzaman, S. N. Kumar
{"title":"Designing high power RF amplifiers: An analytic approach","authors":"M. M. De Souza, M. Rasheduzzaman, S. N. Kumar","doi":"10.1109/ICCDCS.2014.7016181","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016181","url":null,"abstract":"An analytic approach to prototype RF Power Amplifiers is demonstrated at 3.5 GHz. The approach can predict not only matching impedances to high accuracy, but also the small signal gain and PldB in comparison to measurement. Moreover, the method allows a simple and direct route to correlate device and process technology to RF system performance currently unfeasible via TCAD modelling. The work is motivated by the objective to facilitate a higher efficiency, lower cost to prototyping, particularly where vendor models from some manufacturers are still under development.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129156880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors 工艺参数缩放对渐变通道SOI nMOSFET晶体管模拟性能的影响
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016159
R. Assalti, M. Pavanello, M. de Souza, D. Flandre
{"title":"Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors","authors":"R. Assalti, M. Pavanello, M. de Souza, D. Flandre","doi":"10.1109/ICCDCS.2014.7016159","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016159","url":null,"abstract":"This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124715135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Formation and characterization of tin layers for metal gate electrodes of CMOS capacitors CMOS电容器金属栅电极用锡层的形成与表征
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016171
A. S. Garcia, J. A. Diniz, J. Swart, L. Lima, M. V. Puydinger dos Santos
{"title":"Formation and characterization of tin layers for metal gate electrodes of CMOS capacitors","authors":"A. S. Garcia, J. A. Diniz, J. Swart, L. Lima, M. V. Puydinger dos Santos","doi":"10.1109/ICCDCS.2014.7016171","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016171","url":null,"abstract":"In this study, ultrathin films (thickness of less than 20 nm) of titanium nitride (TiN) to be used as gate electrodes for CMOS (Complementary Metal Oxide Semiconductor) technology were obtained. These ultrathin films were obtained by electron beam evaporation of ultrathin layers (1 or 2 nm thick) of titanium (Ti) followed by ECR (Electron Cyclotron Resonance) plasma nitridation of nitrogen (N2). After deposition and nitridation of the titanium, in order to prevent oxidation of the films, in the same nitriding ECR reactor, a-Si:H (hydrogenated amorphous silicon) films were deposited by CVD (Chemical Vapor Deposition) using SiH4/Ar plasma. These films of a-Si:H were implanted with phosphorus (P+) and annealed by rapid thermal annealing to turn them n+ dopped and polycrystalline. Thus, MOS metal gate electrodes were formed with n+ Poly-Si/TiN structures.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114802147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Transitory recovery time of bio-potential amplifiers that include CMOS pseudo-resistors 含CMOS伪电阻的生物电位放大器的暂态恢复时间
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016169
C. F. Pereira, P. Benko, J. Lucchi, R. Giacomini
{"title":"Transitory recovery time of bio-potential amplifiers that include CMOS pseudo-resistors","authors":"C. F. Pereira, P. Benko, J. Lucchi, R. Giacomini","doi":"10.1109/ICCDCS.2014.7016169","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016169","url":null,"abstract":"In this paper a study of the recovery time after a high-amplitude input transitory voltage is evaluated, for a low-frequency bio-potential amplifier. The importance of this parameter for very small low frequency cut-off circuits relies on the expectation, given by the linear model, that the amplifier may take hundreds of seconds to come out of the saturation state, what could be unacceptable for real applications. Actually, the nonlinearity of some components that are used in the amplifiers feedback circuit, particularly the CMOS pseudo-resistors, contributes to the reduction of the recovery time. The bio-amplifier evaluation was carried out using a typical two-stage circuit topology. The circuit behavior is evaluated for several CMOS pseudo-resistor values, with nMOS and pMOS solutions, using a new pseudo-resistor non-linear model. The frequency response target is a 10KHz bandwidth with low frequency cutoff of 1Hz (-3dB). The behavior was evaluated using a MOSIS SCN05 technology (0.5μm) and BSIM3V3.1 models on Eldo™ SPICE analog simulator.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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