B. Cardoso Paz, M. Pavanello, Fernando Avila, A. Cerdeira
{"title":"双栅无结晶体管的短沟道连续模型","authors":"B. Cardoso Paz, M. Pavanello, Fernando Avila, A. Cerdeira","doi":"10.1109/ICCDCS.2014.7016158","DOIUrl":null,"url":null,"abstract":"This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Short channel continuous model for double-gate junctionless transistors\",\"authors\":\"B. Cardoso Paz, M. Pavanello, Fernando Avila, A. Cerdeira\",\"doi\":\"10.1109/ICCDCS.2014.7016158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.\",\"PeriodicalId\":200044,\"journal\":{\"name\":\"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCDCS.2014.7016158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2014.7016158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Short channel continuous model for double-gate junctionless transistors
This work aims to present a continuous model of the drain current for short channel double-gate junctionless transistors, from a charge-based model for long channel double-gate devices. The proposed model is based on the influence of the drain bias in the channel potential and the reduction of the effective channel length in saturation regime, for short channel transistors. To model validation it will be used three dimensional numerical simulations.