工艺参数缩放对渐变通道SOI nMOSFET晶体管模拟性能的影响

2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI:10.1109/ICCDCS.2014.7016159

R. Assalti, M. Pavanello, M. de Souza, D. Flandre

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引用次数: 4

摘要

本文旨在通过二维数值模拟和实验结果，分析工艺参数降阶对梯度通道FD SOI nMOSFET晶体管模拟性能的影响。前门氧化物和硅膜厚度、沟道掺杂浓度、总沟道和轻掺杂区域长度都可以改变，以达到最高的本征电压增益。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

This paper aims at analyzing, through two-dimensional numerical simulations and experimental results, the influence of technological parameters downscaling on the analog performance of Graded-Channel FD SOI nMOSFET transistors. Front gate oxide and silicon film thicknesses, channel doping concentration, total channel and lightly doped region lengths have been varied to target the highest intrinsic voltage gain.

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2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

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