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Electrochemical response for lithium ion battery of LiFePo4-C nanocomposite cathode LiFePo4-C纳米复合阴极锂离子电池的电化学响应
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016146
Arun Kumar, R. Nazario, M. Toma
{"title":"Electrochemical response for lithium ion battery of LiFePo4-C nanocomposite cathode","authors":"Arun Kumar, R. Nazario, M. Toma","doi":"10.1109/ICCDCS.2014.7016146","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016146","url":null,"abstract":"LiFePO4/C nanoparticles were synthesized by solid state reaction and controlled cooling rates. LiFePO4/C samples showed olivine phase irrespective of the cooling rate. However, the average particle sizes significantly changed with the cooling rate; the particle size was 200 nm when prepared by slow cooling (10°C/min) and 120 nm by fast cooling (air quenching). Assembled coin cells exhibited first discharge capacities of 143.7 mAh/g and 159.5 mAh/g at C/10 respectively for the slow cooled and fast cooled samples; fast cooling enhanced the specific capacity. However, at high 4C-rate the specific capacity reduced to 42 mAh/g and 81 mAh/g for both slow and fast cooled samples. In short, cooling rates during the synthesis of LiFePO4/C cathode material can be used to tailor the battery performance.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an acquisition system for bioelectric signals (heart) using an embedded system in FPGA platform 基于FPGA平台的嵌入式生物电信号(心脏)采集系统的设计
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016160
R. Soto-Camacho, M. Vargas, S. Vergara, F. Reyes, A. Palomino, M. Vargas, J. Rodriguez
{"title":"Design of an acquisition system for bioelectric signals (heart) using an embedded system in FPGA platform","authors":"R. Soto-Camacho, M. Vargas, S. Vergara, F. Reyes, A. Palomino, M. Vargas, J. Rodriguez","doi":"10.1109/ICCDCS.2014.7016160","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016160","url":null,"abstract":"At present there are various measuring devices or instruments that acquire the electrical activity of the heart (ECGs), but make a proper measurement, models the signs are printed directly on sheets of graph paper, unable to save the information for later analysis. In this work we make the development of a bioelectric signal acquisition, in this case focused on the signals emitted by the heart to be acquired and stored on a computer. The system is based on a card bioelectric signal acquisition developed in the Maestria en Ciencias de la Electrónica de la Facultad de Ciencias de la Electronica en la BUAP called MIOCARD 1.0 [1]. This card has already implemented a 2-channel electromyograph, and this paper focuses on describing the design of a electrocardiography for the acquisition of the 12 signals that can be obtained from the heart. The card is based on a brand ALTERA FPGA family CycloneII (EP2C8Q208C7) and communication to and from the computer via the protocol is PCI (Peripheral Component Interconnect).","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117089643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of hot carrier degradation on MOSFET small-signal input, output, and transmission features 热载流子退化对MOSFET小信号输入、输出和传输特性的影响
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016163
Daniel Garcia-Garcia, V. Vega-Gonzalez, R. Torres‐Torres, E. Gutiérrez-D.
{"title":"Impact of hot carrier degradation on MOSFET small-signal input, output, and transmission features","authors":"Daniel Garcia-Garcia, V. Vega-Gonzalez, R. Torres‐Torres, E. Gutiérrez-D.","doi":"10.1109/ICCDCS.2014.7016163","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016163","url":null,"abstract":"An analysis of the level of hot carrier (HC) degradation caused in sub-100 nm n-type MOSFETs operated from DC up to 20 GHz, is introduced. The analysis comes accompanied with experimental results. The degradation process is done through the application of controlled DC currents at well defines periods of time. The recorded S-parameters before and after DC degradation allows the observation of the corresponding changes in the transmission and reflection features, as well as in the intrinsic channel resistance and the transconductance. This analysis is relevant for power CMOS amplifiers operating in the RF frequency regime.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs 地平面对增强动态阈值UTBB SOI nmosfet的影响
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016149
K. Sasaki, M. Manini, J. Martino, M. Aoulaiche, E. Simoen, L. Witters, C. Claeys
{"title":"Ground plane influence on enhanced dynamic threshold UTBB SOI nMOSFETs","authors":"K. Sasaki, M. Manini, J. Martino, M. Aoulaiche, E. Simoen, L. Witters, C. Claeys","doi":"10.1109/ICCDCS.2014.7016149","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016149","url":null,"abstract":"This paper investigates the ground plane influence on Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT) operation (V<sub>B</sub>=V<sub>G</sub>) over the conventional one (V<sub>B</sub>=0V). The ground plane in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (V<sub>B</sub>=k×V<sub>G</sub>) and the inverse eDT mode (V<sub>G</sub>=k×V<sub>B</sub>) were also considered and compared to the other configurations. The presence of the Ground Plane region in all DT configurations results in superior DC parameters like on-current/off-current ratio, a steeper subthreshold slope and a higher transconductance.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design, simulation and fabrication of a hollow core ARROW waveguide in glass substrate for optofluidic applications 光流体应用玻璃基板中空箭头波导的设计、模拟与制造
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016174
E. Melo, I. Abe, M. A. Alvarado, M. Carrenõ, M. I. Alayo
{"title":"Design, simulation and fabrication of a hollow core ARROW waveguide in glass substrate for optofluidic applications","authors":"E. Melo, I. Abe, M. A. Alvarado, M. Carrenõ, M. I. Alayo","doi":"10.1109/ICCDCS.2014.7016174","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016174","url":null,"abstract":"The antiresonant reflecting optical waveguide (ARROW) with hollow core and liquid core are one of the most promising technologies in Lab-on-a-Chips and optofluidic research. Motivated by this, in this paper we present the design, simulation and fabrication processes of hollow core ARROW built in Corning glass substrates and utilizing Si3N4/SiO2 PECVD antiresonant reflecting multilayer films on the channel wall. Details about the TMM/FDM methodology developed for the simple and fast design of ARROW waveguides built with multilayer dielectric thin films deposited over rounded microchannels in glass substrates are exhibited. The preliminary results confirm the light confinement in the hollow core region of the fabricated waveguide structure but further experiment are needed to fully characterize the devices.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115220227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plasmonics for optical communications: The use of graphene for optimizing coupling efficiency 光通信等离子体:石墨烯用于优化耦合效率
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016180
D. Mynbaev, V. Sukharenko
{"title":"Plasmonics for optical communications: The use of graphene for optimizing coupling efficiency","authors":"D. Mynbaev, V. Sukharenko","doi":"10.1109/ICCDCS.2014.7016180","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016180","url":null,"abstract":"Application of plasmonics in optical communications has recently attracted significant research interest in the hope of overcoming the big mismatch between the footprints of electronic and photonic integrated circuits. This hope is based on the unique properties of the plasmonic devices, such as the confinement of light into subwavelength dimension. which enables breaking the diffraction limit and creating a strong field enhancement and the potential to combine the best properties of both electronic and photonic words thanks to the natural interaction between photons and electrons in excitation of surface plasmon polaritons (SPPs). Such a breakthrough would lead to the development of new types of opto-electronic devices. One the main problems to be solved for this application to succeed is the coupling efficiency of incident light. This paper reviews our investigation of the various approaches to increasing the coupling efficiency and shows how the use of graphene can significantly improve this efficiency.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123935844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Equivalent circuit and analytical representation of double resonances in PCB striplines PCB带状线中双共振的等效电路及解析表示
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016165
G. Romo, G. Méndez-Jerónimo, R. Torres‐Torres, C. Nwachukwu
{"title":"Equivalent circuit and analytical representation of double resonances in PCB striplines","authors":"G. Romo, G. Méndez-Jerónimo, R. Torres‐Torres, C. Nwachukwu","doi":"10.1109/ICCDCS.2014.7016165","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016165","url":null,"abstract":"Striplines present more than one resonance around frequencies at which multiples of half the wavelength of the propagated signals equal the spacing between fiber yarns along their path within a PCB. In this paper, a method to obtain the effective propagation constant and characteristic impedance considering this undesired effect is proposed. This allows the proper representation of striplines to assess the negative impact of the resonances in the performance of inter-layer interconnects on PCB. Data obtained using the new method shows excellent correlation with measurements up to 50 GHz. Furthermore, a methodology to implement the corresponding equivalent circuit of these interconnects is also shown, which allows to point out the simplicity and convenience of using the proposed method at microwave operation frequencies.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116471467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature 垂直纳米线tfet的早期电压和本征电压增益随温度的变化
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016154
M. D. V. Martino, F. Neves, P. Agopian, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, A. Thean, C. Claeys
{"title":"Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature","authors":"M. D. V. Martino, F. Neves, P. Agopian, J. Martino, A. Vandooren, R. Rooyackers, E. Simoen, A. Thean, C. Claeys","doi":"10.1109/ICCDCS.2014.7016154","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016154","url":null,"abstract":"The goal of this work is to study parameters related to the analog performance of tunnel field effect transistors (TFETs). The obtained results have been analyzed in terms of temperature variation (ranging from 25°C to 150°C) and source composition (Sh-xGex and 100% Si). The first part is focused on characteristic curves of the drain current as a function of gate voltage and drain voltage. Next step highlights the Early voltage and the ratio of transconductance and drain current, since these parameters lead to the extraction of the intrinsic voltage gain. Performing a temperature analysis, different trends have been obtained depending on the device. For instance, devices with 100% Si source and non-abrupt junction profile present the lowest gain at room temperature, but the best results for temperatures higher than 100°C. The suitability of TFETs for analog applications has been discussed based on these results.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127061509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fin width influence on analog performance of SOI and bulk FINFETs 翅片宽度对SOI和块状finfet模拟性能的影响
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016150
A. Oliveira, P. Agopian, J. Martino, E. Simoen, C. Claeys
{"title":"Fin width influence on analog performance of SOI and bulk FINFETs","authors":"A. Oliveira, P. Agopian, J. Martino, E. Simoen, C. Claeys","doi":"10.1109/ICCDCS.2014.7016150","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016150","url":null,"abstract":"This paper presents an experimental comparison of the analog performance between a triple-gate FinFET fabricated on Bulk (BFF) and on Silicon-On-Insulator - SOI (SFF) substrates. This comparison was performed based on the drain current, subthreshold swing, transconductance, output conductance and finally the intrinsic voltage gain. For narrow fin width, the SFF presents better performance than BFF, while for wider fins, the BFF showed to be more optimized than SFF, due to the existence of a parasitic back transistor in the SOI device.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133753093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The effect of X-Ray radiation on DIBL for standard and strained triple-gate SOI MuGFETs x射线辐射对标准和应变三栅SOI mugfet DIBL的影响
2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS) Pub Date : 2014-04-02 DOI: 10.1109/ICCDCS.2014.7016153
C. Bordallo, F. F. Teixeira, M. Silveira, J. Martino, P. Agopian, E. Simoen, C. Claeys
{"title":"The effect of X-Ray radiation on DIBL for standard and strained triple-gate SOI MuGFETs","authors":"C. Bordallo, F. F. Teixeira, M. Silveira, J. Martino, P. Agopian, E. Simoen, C. Claeys","doi":"10.1109/ICCDCS.2014.7016153","DOIUrl":"https://doi.org/10.1109/ICCDCS.2014.7016153","url":null,"abstract":"This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (OIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation, based on the subthreshold region characteristics studied. For pMuGFETs, radiation is not always harmful, because it reduces the leakage current, improving the subthreshold swing of the drain current. However, for devices that are less sensitive to this leakage current, the radiation-induced interface traps become the predominant damage mechanism.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133178740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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