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2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)最新文献

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A Surface-Micromachined Levitating MEMS Speaker 表面微机械悬浮式MEMS扬声器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842083
Antoine Verreault, Paul-Vahé Cicek, A. Robichaud
{"title":"A Surface-Micromachined Levitating MEMS Speaker","authors":"Antoine Verreault, Paul-Vahé Cicek, A. Robichaud","doi":"10.1109/NEWCAS52662.2022.9842083","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842083","url":null,"abstract":"This paper presents the design and simulation of a levitating MEMS speaker. The device is composed of a levitating membrane actuated through electrostatic forces using several electrodes and a control system. The absence of supporting anchors allows for a drastic reduction of damping losses and therefore promises higher power efficiency. Simulation results indicate very promising performance.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Baseband TIA Design Using Inversion Coefficient MOSFET Model in CMOS 28nm 基于反转系数MOSFET模型的28nm CMOS基带TIA设计
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842093
Léo Lançon, Hugo Vallée, G. Montoriol, Fabien Brunelli, T. Taris
{"title":"Baseband TIA Design Using Inversion Coefficient MOSFET Model in CMOS 28nm","authors":"Léo Lançon, Hugo Vallée, G. Montoriol, Fabien Brunelli, T. Taris","doi":"10.1109/NEWCAS52662.2022.9842093","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842093","url":null,"abstract":"This paper presents a design methodology to size a transimpedance amplifier for an automotive radar receiver. Based on the Enz-Krummenacher-Vittoz (EKV) MOSFET model, it presents the essential equations to develop a small-signal model featuring a limited number of parameters, which can be exploited to quickly explore the different design optimums of a circuit. Post-layout simulations are presented to validate the model and the methodology. The designed TIA presents a gain of 65 dBΩ, a bandwidth of 80 MHz, an input impedance of 74 Ω and input-referred noise of 50 yA2.Hz−1.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128874938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A broadband transceiver ASIC for X-nuclei NMR spectroscopy in 0.13 µm BiCMOS 一种用于0.13µm BiCMOS中x核核波谱的宽带收发器ASIC
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842238
Frederik Dreyer, Daniel Krüger, Sander Baas, A. Velders, J. Anders
{"title":"A broadband transceiver ASIC for X-nuclei NMR spectroscopy in 0.13 µm BiCMOS","authors":"Frederik Dreyer, Daniel Krüger, Sander Baas, A. Velders, J. Anders","doi":"10.1109/NEWCAS52662.2022.9842238","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842238","url":null,"abstract":"In this paper, we present a fully-integrated transceiver ASIC (NMR-on-a-chip) for multi-nuclei nuclear magnetic resonance (NMR) measurements with operating frequencies up to 770 MHz. The NMR-on-a-chip transceiver co-integrates a low-IF receiver, consisting of a low-noise amplifier, quadrature down-conversion mixers followed by intermediate-frequency variable gain amplifiers, a power amplifier, and a frequency generation block. The ASIC is realized in a 0.13 µm SiGe BiCMOS technology and occupies a total chip area of 1100×900 µm2. The power amplifier has a maximum peak-to-peak output current of ITX,pp = 210 mA. The receiver chain has a maximum conversion gain of ARX = 66 dB with a minimum input-referred noise of ${v_{{text{n,min}}}} = 610{text{ pV}}/sqrt {{text{Hz}}} $. The chip performance is also verified in the target NMR application, in which the presented system achieves a state-of-the-art normalized spin sensitivity of $8.3 times {10^{17}}{text{spins}}/sqrt {Hz} cdot {{text{T}}^2}{text{m}}$.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS 28纳米CMOS中嵌入尖峰压缩的49通道神经记录ASIC的初步结果
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842184
W. Lemaire, Esmaeil Ranjbar Koleibi, Takwa Omrani, Maher Benhouria, K. Koua, Charles Quesnel, Louis-Philippe Gauthier, Jérémy Ménard, Keven Gagnon, S. Roy, R. Fontaine
{"title":"Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS","authors":"W. Lemaire, Esmaeil Ranjbar Koleibi, Takwa Omrani, Maher Benhouria, K. Koua, Charles Quesnel, Louis-Philippe Gauthier, Jérémy Ménard, Keven Gagnon, S. Roy, R. Fontaine","doi":"10.1109/NEWCAS52662.2022.9842184","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842184","url":null,"abstract":"Neural interfaces allow better understanding of the brain by precisely measuring its activity, down to the level of single neurons. However, recording a high number of neurons requires a high number of analog-to-digital converters that generate a massive amount of data, making wireless transmission difficult. To solve this, we designed a neural recording application specific integrated circuit (ASIC) comprising a single ramp analog-to-digital converter (ADC) and a spike-by-spike digital compression circuit based on principal component analysis (PCA). The ASIC comprises 49 channels (each occupying an on-chip area of 50 × 60 µm2), a simulated noise of 12.3 µV RMS, and a power consumption of 4.6 µW. The circuit measures 1370 × 1370 µm2 and consumes 828 µW. This paper presents the architecture and preliminary performance results of the neural recording ASIC and its compression circuit.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NB-IoT High Linear Doherty Amplifier with Active Balun 带有源平衡的NB-IoT高线性多尔蒂放大器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842261
Tristan Lecocq, E. Kerhervé, J. Pham
{"title":"NB-IoT High Linear Doherty Amplifier with Active Balun","authors":"Tristan Lecocq, E. Kerhervé, J. Pham","doi":"10.1109/NEWCAS52662.2022.9842261","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842261","url":null,"abstract":"This paper presents a Doherty power amplifier with an enhanced power back-off efficiency and a high linearity using an adaptive bias circuit. The silicon area reduction is achieved with an active balun driver topology. The operating frequency range is 1.49GHz to 2.17GHz for NB-IoT applications. The post layout simulations (PLS) show a maximum output power of 31.6dBm with a peak PAE of 35.3% at 1.85GHz. The efficiency drops to 28% at 6dB back-off. The robustness to the 2:1 SWR achieves a variation in Gain and Psat of 3dB and 0.8dB, respectively.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Triple-Mode Programmable 12V Charge Pump for High Dynamic Range Photodiode Array Biasing 用于高动态范围光电二极管阵列偏置的三模可编程12V电荷泵
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842089
Mostafa Toubar, S. Ibrahim
{"title":"A Triple-Mode Programmable 12V Charge Pump for High Dynamic Range Photodiode Array Biasing","authors":"Mostafa Toubar, S. Ibrahim","doi":"10.1109/NEWCAS52662.2022.9842089","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842089","url":null,"abstract":"This paper proposes a programmable 12V charge pump output supplied from a 2.5V supply in 65nm CMOS technology. The programmable charge pump consists of a unit stage that can work in both charging and discharging modes. This unit stage is cascaded to provide the programmable high voltage required for biasing different types of photodiodes. The charge pump exhibits a reliable voltage range extending from 2V to 12V in 65nm bulk CMOS technology. The large voltage range is used to bias different types of photodiodes to achieve a high dynamic range for the photodetector array. The proposed charge pump, with an area of 0.07 mm2, adds no extra mask cost as the devices used are standard thick-oxide devices. The charge pump drives a 100pF load capacitor at 50 kHz switching frequency between the three available modes, namely, Single Photon Avalanche Diode (SPAD), Avalanche Photodiode (APD), and Linear Photodiode (PD) with 64% power efficiency when consuming 120μA..","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115505588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups 使用多个比较器组改进基于订单统计的Flash ADC性能
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842172
T. Kitamura, Mahfuzul Islam, T. Hisakado, O. Wada
{"title":"Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups","authors":"T. Kitamura, Mahfuzul Islam, T. Hisakado, O. Wada","doi":"10.1109/NEWCAS52662.2022.9842172","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842172","url":null,"abstract":"Due to offset voltage variation, power consumption increases significantly to ensure sufficient performance of flash ADCs. As a solution, statistical selection of comparators based on the order of offset voltages has been proposed. This method achieves at-speed on-chip calibration without the need for analog measurements. To increase the linearity and SNDR under the same power consumption, this paper proposes to use multiple comparator groups with different sizing to tune a distribution of offset voltage. We design and fabricate two ADCs, one with only single comparator group and the other with three comparator groups, in a 65 nm bulk general-purpose process. We confirm the ADC operations at a 1 GS/s and validate order statistic based comparator selection. We then confirm INL improvement by using multiple groups under the same number of total comparators.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130048899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology 新兴负电容晶体管技术中缓解功率侧通道攻击的新方法
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842186
Shubham Kumar, Swetaki Chatterjee, Chetan Kumar Dabhi, H. Amrouch, Y. Singh Chauhan
{"title":"A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology","authors":"Shubham Kumar, Swetaki Chatterjee, Chetan Kumar Dabhi, H. Amrouch, Y. Singh Chauhan","doi":"10.1109/NEWCAS52662.2022.9842186","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842186","url":null,"abstract":"Power side-channel (PSC) attacks have recently gained popularity in breaking into cyber-physical systems due to their non-invasiveness and proven effectiveness. In the CMOS circuit, the power dissipation when output transitions from ‘0' to ‘1' is different compared to the transition from ‘1' to ‘0'. The difference in power consumption results in input-dependent correlation, used for PSC to infer secret keys. This is the first work to investigate the impact of PSC on NCFET at the device level. We demonstrate using Gate Work Function engineering to mitigate PSC attacks effectively for the first time.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122526278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient FPGA overlay for MPI-2 RMA parallel applications MPI-2 RMA并行应用的高效FPGA覆盖
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842139
Mathieu Leonel Mba, R. C. G. N. Ewo, J. Denoulet, Paulin Melatagia Yonta, B. Granado
{"title":"An efficient FPGA overlay for MPI-2 RMA parallel applications","authors":"Mathieu Leonel Mba, R. C. G. N. Ewo, J. Denoulet, Paulin Melatagia Yonta, B. Granado","doi":"10.1109/NEWCAS52662.2022.9842139","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842139","url":null,"abstract":"Design productivity issues, including difficult hardware design and long compile times, are major barriers to the widespread adoption of FPGA-based accelerations in main-stream computing. Enabling virtualized execution of software and hardware tasks on FPGA platforms make them more accessible would to application developers accustomed to software API abstractions such as MPI and fast development cycles. In this work, we show that the MATIP platform provides a viable and efficient FPGA overlay architecture for the design of MPI parallel applications. We support this with a parallel model implementation of a feature extraction algorithm for tone language recognition, which is shown to be at least 7 times more efficient than a C++ MPI-2 RMA implementation of the same parallel model on a CPU and almost 3 times more efficient than a naive FPGA IP implementation.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133661645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An FPGA Implementation of A Portable DNA Sequencing Device Based on RISC-V 基于RISC-V的便携式DNA测序仪的FPGA实现
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842014
Zhongpan Wu, Karim Hammad, Abel Beyene, Yunus Dawji, E. Ghafar-Zadeh, S. Magierowski
{"title":"An FPGA Implementation of A Portable DNA Sequencing Device Based on RISC-V","authors":"Zhongpan Wu, Karim Hammad, Abel Beyene, Yunus Dawji, E. Ghafar-Zadeh, S. Magierowski","doi":"10.1109/NEWCAS52662.2022.9842014","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842014","url":null,"abstract":"Miniature and mobile DNA sequencers are steadily growing in popularity as effective tools for genetics research. As basecalling algorithms continue to evolve, basecalling poses a serious challenge for small computing devices despite its increasing accuracy. Although general-purpose computing chips such as CPUs and GPUs can achieve fast results, they are not energy efficient enough for mobile applications. This paper presents an innovative solution, a basecalling hardware architecture based on RISC-V ISA, and after validation with our custom FPGA verification platform, it demonstrates a 1.95x energy efficiency ratio compared to x86. There is also a 38% improvement in energy efficiency ratio compared to ARM. In addition, this study also completes the verification work for subsequent ASIC designs.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128180830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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