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2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)最新文献

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Integrated Self-Interference Suppression for Single Antenna Full-Duplex without Circulator 无环行器单天线全双工集成自干扰抑制
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842266
Yongqian Du, Jiahao Chen, Gui-fang Li, K. Han, Tianxiang Qu, Shibin Liu
{"title":"Integrated Self-Interference Suppression for Single Antenna Full-Duplex without Circulator","authors":"Yongqian Du, Jiahao Chen, Gui-fang Li, K. Han, Tianxiang Qu, Shibin Liu","doi":"10.1109/NEWCAS52662.2022.9842266","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842266","url":null,"abstract":"Full-duplex (FD) enables high spectrum efficiency and dynamic spectrum accessing, although its extensive application is restricted by significant self-interference (SI). In this work, we present a highly integrated, single antenna wideband FD SI suppression solution, targeting for short-range wireless communication. Based on the characteristic of bi-directional signal transparency of N-phase passive mixer, a mixer-first active electrical balance FD SI suppression architecture is proposed. As no costly and space-consuming circulator or duplexer is needed compared with traditional single antenna SI suppression solutions, this work is attractive for cost and area saving. In addition, to alleviate the multi-path SI effect, a two-tap baseband SI suppression is adopted, which also helps broaden the SI suppression bandwidth. The fabricated FD SI suppression RF front-end chip shows a satisfactory SI suppression depth up to 52dB over 30MHz, with a 0.4-1.2GHz operation carrier frequency range.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129814516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ASIP Accelerator for LUT-based Neural Networks Inference 基于lut的神经网络推理的ASIP加速器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842211
Moussa Traore, J. Langlois, J. David
{"title":"ASIP Accelerator for LUT-based Neural Networks Inference","authors":"Moussa Traore, J. Langlois, J. David","doi":"10.1109/NEWCAS52662.2022.9842211","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842211","url":null,"abstract":"Binarized Neural Networks (BNNs) offer the promise of low power and high throughput, but this is difficult to achieve on regular processors. A considerable amount of research has been devoted to mapping BNNs to specialized hardware, especially FPGAs, setting aside the flexibility of instruction-set processors. This paper introduces a configurable VLIW processor with a specialized instruction set to efficiently compute the inference of Look-Up-Table based artificial binary neurons in a single clock cycle. Our experiments show that the processor achieves an increased throughput of 2994 when compared to the inference done on a base processor. ×","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130809734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact Closed-loop EEG/fNIRS Recording and TMS Neuromodulation System 紧凑型闭环EEG/fNIRS记录和TMS神经调节系统
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842210
Ning Li, Jie Yang, M. Sawan
{"title":"Compact Closed-loop EEG/fNIRS Recording and TMS Neuromodulation System","authors":"Ning Li, Jie Yang, M. Sawan","doi":"10.1109/NEWCAS52662.2022.9842210","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842210","url":null,"abstract":"Transcranial magnetic stimulation (TMS) is a clinic-proven neuromodulation technique to treat various neurological and psychological diseases. However, existing TMS devices are bulky, expensive, and open loop. Therefore, they can only be used in fixed locations, and the modulation effects cannot be measured. In this paper, a wearable close-loop neuromodulation system that integrates real-time EEG/fNIRS recording and TMS is proposed. The system’s real-time signal monitoring and analysis function allows the inducing of magnetic stimulation and helps measure its effects after stimulation. The proposed system can measure and analyze 23 channel EEG and 64 channel fNIRS signals simultaneously in real-time. The dimensions of the fabricated TMS device are 330mm × 148mm × 112mm, with peak voltage and current values of 1100 V and 2400A, respectively, resulting in peak magnetic stimulation of 620 mTesla and bidirectional current pulse width of 311 μs.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122962406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-performance Multi-function HMAC-SHA2 FPGA Implementation 高性能多功能HMAC-SHA2 FPGA实现
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842174
Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Akira Tsukamoto, K. Suzaki, C. Pham
{"title":"High-performance Multi-function HMAC-SHA2 FPGA Implementation","authors":"Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Akira Tsukamoto, K. Suzaki, C. Pham","doi":"10.1109/NEWCAS52662.2022.9842174","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842174","url":null,"abstract":"Today, Hash-based Message Authentication Code with Secure Hash Algorithm 2 (HMAC-SHA2) is widely used in modern protocols, such as in Internet Protocol Security (IPSec) and Transport Layer Security (TLS). Many authors proposed their HMAC-SHA2 hardware implementations. Some targeted a high-performance design, while others aimed to satisfy an area constraint. Those implementations are acceptable for applications that require only low-cost or high throughput. However, some applications, such as Software-Defined Networking (SDN), Internet-of-Thing (IoT), and Wireless Sensor Network (WSN), need an efficient design that can satisfy both merits. In this paper, an FPGA implementation is proposed that can operate on multiple HMAC-SHA2 variants without re-synthesize. The proposed architecture achieves high performance with a low-cost area. The experimental results show that it can run up to 380-MHz, more than 4.8 Giga-bit-per-second (Gbps), with fewer resources compared to other similar designs.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"125 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126282586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications 具有高传导损耗降低和快速动态响应的汽车用多相混合升压变换器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842223
V. Nguyen, Xuan-Dien Do, Y. Blaquière, G. Cowan
{"title":"Multi-Phase Hybrid Boost Converter with High Conduction Loss Reduction and Fast Dynamic Response for Automotive Applications","authors":"V. Nguyen, Xuan-Dien Do, Y. Blaquière, G. Cowan","doi":"10.1109/NEWCAS52662.2022.9842223","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842223","url":null,"abstract":"In this paper, the concept of multi-phase hybrid buck and boost converters (MP-HBUC and MP-HBOC), is presented. By using single-phase hybrid buck and boost converters (HBUC and HBOC), the proposed MP-HBUC and MP-HBOC significantly reduce conduction loss as compared to the conventional buck and boost converter (CBUC and CBOC). Thus, the proposed MP-HBUC and MP-HBOC maintain high efficiency at heavy loads. Furthermore, the proposed MP-HBOC achieves a minimum-phase characteristic (without right half-plan zero); therefore, the bandwidth and load transient response of the proposed MP-HBOC can be respectively much wider and faster than a CBOC. Implemented in PSIM with extensive analysis, a two-phase 97.16hybrid boost converter showed a max/min efficiency % and 91.3 %, respectively, over a load current of up to 0.25-10 A at 12 V input, 18 V output voltage. The efficiency improvement is up to 4.95 % at the maximum load. This work can be considered as the very first reported combination of multi-phase and hybrid concepts to design high power-efficient buck/ boost converters for automotive applications.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121143119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results 新型差分脉冲检测系统:原型与实验结果
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842231
Sharath Patil, Bhanu Singh, Raunak M. Borwankar, M. Margala
{"title":"Novel Pulse Detection System Using Differentiation: Prototyping and Experimental Results","authors":"Sharath Patil, Bhanu Singh, Raunak M. Borwankar, M. Margala","doi":"10.1109/NEWCAS52662.2022.9842231","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842231","url":null,"abstract":"Light Detection and Ranging (LiDAR) sensors play an important role in obstacle detection and avoidance in autonomous vehicles. In a Direct Time Of Flight (DTOF) Li-DAR, pulse detection is an important function which is often accomplished using high speed ADCs with sampling rates in the range of 0.5-1 giga samples per second. This poses problems for multi-channel single-chip LiDAR sensors due to area and power requirements of giga sample ADCs. In this paper, experimental results are presented from an implementation of pulse detection using differentiation by employing comparators, a novel method. A prototype for pulse detection mechanism has been implemented on a PCB using an array of sample and hold capacitors followed by a comparator. The performance of a low-area, low-power comparator-based pulse detection has been compared to that of a high-area, high-power ADC-based pulse detection system. The control circuitry and data processing are implemented on a Xilinx ZYNQ-based FPGA. Results of emulation of distance measurement show that the performance of comparator-based system is similar to that of an ADC-based system but potentially with less than 50% of area and power on a single-chip implementation.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121525161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memristor-assisted Background Calibration for Analog-to-Digital Converter 模数转换器的忆阻器辅助背景校正
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842108
Zhaoguang Si, Chao-Hsiang Wang, Adil Malik, Shiwei Wang, T. Prodromakis, C. Papavassiliou
{"title":"Memristor-assisted Background Calibration for Analog-to-Digital Converter","authors":"Zhaoguang Si, Chao-Hsiang Wang, Adil Malik, Shiwei Wang, T. Prodromakis, C. Papavassiliou","doi":"10.1109/NEWCAS52662.2022.9842108","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842108","url":null,"abstract":"This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADC). A R-2R digital-to-analog converter (DAC) was implemented with a memristor array and other peripheral circuits. The background calibration detects the error caused by DAC mismatch and corrects it by adjusting the memristor’s memristance1 in a feedback loop. The implemented circuit takes advantage of the memristor’s small area and multi-state switching property. Simulation results show the feasibility of using memristors to correct mismatch in high-resolution ADC design. The proposed system has been designed in a TSMC 180nm process. Memristors will be laid on the top of the chip via Metal 5 and Metal 6.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127610990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 400V Gate Driver with Complementary Slope Sensing ZVS Detector and High Voltage Level Shifter for Full-Bridge Phase-Shifted Converters 一种400V栅极驱动器，具有互补斜率传感ZVS检测器和高压电平移位器，用于全桥移相转换器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842253
Wei Zhu, Arindam Mishra, Arijit Karmakar, V. D. Smedt
{"title":"A 400V Gate Driver with Complementary Slope Sensing ZVS Detector and High Voltage Level Shifter for Full-Bridge Phase-Shifted Converters","authors":"Wei Zhu, Arindam Mishra, Arijit Karmakar, V. D. Smedt","doi":"10.1109/NEWCAS52662.2022.9842253","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842253","url":null,"abstract":"This paper presents an integrated synchronous gate driver with complementary slope sensing zero voltage switching detector (CSSZVSD) and high voltage level shifter (HVLS) to enable phase-shifted full-bridge (PSFB) dc-dc converters with ZVS. The proposed CSSZVSD not only achieves a higher efficiency by minimizing the reverse conduction loss and the switching loss of the power FETs but also eliminates the converter potential short-circuit risk. The proposed HVLS in the gate driver with dynamically tailed current and noise cancellation block improves the driver efficiency and enhances the converter reliability. Implemented in a 1-µm 650V Trench Isolated BCD process, the proposed 400V synchronous gate driver was demonstrated by a GaN-based pulse width modulation ZVS PSFB isolated dc-dc bus converter.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134118053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS 28纳米CMOS中嵌入尖峰压缩的49通道神经记录ASIC的初步结果
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842184
W. Lemaire, Esmaeil Ranjbar Koleibi, Takwa Omrani, Maher Benhouria, K. Koua, Charles Quesnel, Louis-Philippe Gauthier, Jérémy Ménard, Keven Gagnon, S. Roy, R. Fontaine
{"title":"Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS","authors":"W. Lemaire, Esmaeil Ranjbar Koleibi, Takwa Omrani, Maher Benhouria, K. Koua, Charles Quesnel, Louis-Philippe Gauthier, Jérémy Ménard, Keven Gagnon, S. Roy, R. Fontaine","doi":"10.1109/NEWCAS52662.2022.9842184","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842184","url":null,"abstract":"Neural interfaces allow better understanding of the brain by precisely measuring its activity, down to the level of single neurons. However, recording a high number of neurons requires a high number of analog-to-digital converters that generate a massive amount of data, making wireless transmission difficult. To solve this, we designed a neural recording application specific integrated circuit (ASIC) comprising a single ramp analog-to-digital converter (ADC) and a spike-by-spike digital compression circuit based on principal component analysis (PCA). The ASIC comprises 49 channels (each occupying an on-chip area of 50 × 60 µm2), a simulated noise of 12.3 µV RMS, and a power consumption of 4.6 µW. The circuit measures 1370 × 1370 µm2 and consumes 828 µW. This paper presents the architecture and preliminary performance results of the neural recording ASIC and its compression circuit.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NB-IoT High Linear Doherty Amplifier with Active Balun 带有源平衡的NB-IoT高线性多尔蒂放大器
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842261
Tristan Lecocq, E. Kerhervé, J. Pham
{"title":"NB-IoT High Linear Doherty Amplifier with Active Balun","authors":"Tristan Lecocq, E. Kerhervé, J. Pham","doi":"10.1109/NEWCAS52662.2022.9842261","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842261","url":null,"abstract":"This paper presents a Doherty power amplifier with an enhanced power back-off efficiency and a high linearity using an adaptive bias circuit. The silicon area reduction is achieved with an active balun driver topology. The operating frequency range is 1.49GHz to 2.17GHz for NB-IoT applications. The post layout simulations (PLS) show a maximum output power of 31.6dBm with a peak PAE of 35.3% at 1.85GHz. The efficiency drops to 28% at 6dB back-off. The robustness to the 2:1 SWR achieves a variation in Gain and Psat of 3dB and 0.8dB, respectively.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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