2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)最新文献

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Artifact-Recovery in Neuromodulators using Tunable High-Pass Corners 使用可调高通角的神经调节剂的伪影恢复
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842066
Stefan Reich, D. Fritschi, Mark A. Sporer, M. Ortmanns
{"title":"Artifact-Recovery in Neuromodulators using Tunable High-Pass Corners","authors":"Stefan Reich, D. Fritschi, Mark A. Sporer, M. Ortmanns","doi":"10.1109/NEWCAS52662.2022.9842066","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842066","url":null,"abstract":"In neuromodulation systems, stimulation causes artifacts which are orders of magnitude larger than the recorded neural signal. Several recent publications have proposed recorder front-ends with high dynamic range to cope with stimulation artifacts, thereby avoiding blanking switches and the resulting recorder blind-time. However, this usually comes at the cost of limited first-stage amplification due to signal swing requirements, thus degrading the noise efficiency factor (NEF). In this paper, we propose to instead combine blanking switches with a tuning mechanism on the pseudo-resistor based high-pass corner frequency of the frontend. This allows to temporarily increase the settling speed during artifact-recovery, such that undisturbed recording can commence few tens of milli-seconds after e.g., a stimulation event. The artifact-recovery scheme is demonstrated using an integrated state-of-the-art neuromodulator, and in-vitro measurements are presented to validate its usability.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122603823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems 安全关键系统的高效调度、映射和内存带宽分配
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842219
Alexy Torres Aurora Dugo, Jean-Baptiste Lefoul, Aymen Ben-Salem, Serge Harnois, F. Magalhães, G. Nicolescu
{"title":"Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems","authors":"Alexy Torres Aurora Dugo, Jean-Baptiste Lefoul, Aymen Ben-Salem, Serge Harnois, F. Magalhães, G. Nicolescu","doi":"10.1109/NEWCAS52662.2022.9842219","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842219","url":null,"abstract":"In safety-critical multi-core architectures, isolation becomes more challenging as multiple components are shared between the cores, which generates delays in execution time called interferences. To reduce buses contention, it is important to limit the bandwidth allocated to each application. Current state-of-the-art solutions for bus budgeting allocation are not scalable and do not provide the correct level of flexibility to model complex systems. To cope with these challenges, we propose a novel heuristic to generate the schedule, mapping and bus budget allocation. We achieve scalable execution times up to 45 times faster compared to the state of the art. We further introduce real-life constraints such as application dependencies, forced mapping and release time. Compared to the state of the art, our approach is applicable in complex systems.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Wideband Low-Power Current-Reuse RF-to-BB Receiver Using a Clock Strategy Technique 基于时钟策略技术的宽带低功耗电流复用射频- bb接收机
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842165
A. Abbasi, Amirhossein Moshrefi, F. Nabki
{"title":"A Wideband Low-Power Current-Reuse RF-to-BB Receiver Using a Clock Strategy Technique","authors":"A. Abbasi, Amirhossein Moshrefi, F. Nabki","doi":"10.1109/NEWCAS52662.2022.9842165","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842165","url":null,"abstract":"A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end that employs a clock strategy is proposed to support software-defined radios (SDRs). It includes a capacitively cross-coupled common-gate low noise transconductance amplifier (LNTA) to amplify and convert the RF voltage to a current, a passive mixer to down-convert the RF current at 4 × the local-oscillator (LO) frequency to the intermediate frequency (IF) current using a clock strategy, an active-inductor (AI) technique to improve the noise-figure (NF) performance, and a transimpedance amplifier (TIA) to convert the IF current to a voltage at the output. To achieve low power consumption the receiver features: current-reuse between the LNTA and the BB circuits; current-mode harmonic recombination at the output of the passive mixer; and a clock strategy to reduce the dynamic power consumption of the clock generation for the dividers and the LO buffers. The proposed receiver is implemented in 22-nm CMOS technology and occupies an active area of 0.13mm2. In the nominal condition, at an IF of 10MHz and an RF of 2.4GHz, it achieves a voltage gain of 36dB, a double-sideband (DSB) noise figure (NF) of 5.2dB, S11 of less than −10dB and an IIP3 of −18.5dBm while consuming 2.44mA from a 1.2V supply voltage.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliable Power Efficient Systems through Run-time Reconfiguration 通过运行时重新配置的可靠节能系统
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9841986
Nahla El-Araby, A. Jantsch
{"title":"Reliable Power Efficient Systems through Run-time Reconfiguration","authors":"Nahla El-Araby, A. Jantsch","doi":"10.1109/NEWCAS52662.2022.9841986","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9841986","url":null,"abstract":"We propose a methodology for optimizing the reliability, power, area, and performance of Field Programmable Gate Array (FPGA)-based systems at run time based on dynamic reconfiguration. A partial reconfiguration manager is designed to switch between different versions of the design according to real operating conditions. Reliability, Power, area, and performance are factors used for selecting the design version to be configured. Power and Reliability conditions are assessed through monitoring the system power state and the environment radiations with a radiation sensor, respectively. The experimental results show 40% reduction in power consumption while keeping an average reliability of 99.5%.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115866564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience 一种用于直流开关的MEMS电热致动器,用于电源开关应用和高电压弹性
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842102
Abdurrashid Hassan Shuaibu, F. Nabki, Y. Blaquière
{"title":"A MEMS Electrothermal Actuator Designed for a DC Switch Aimed at Power Switching Applications and High Voltage Resilience","authors":"Abdurrashid Hassan Shuaibu, F. Nabki, Y. Blaquière","doi":"10.1109/NEWCAS52662.2022.9842102","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842102","url":null,"abstract":"This work presents the design and fabrication of a chevron (V-shaped) type electro-thermally actuated micro-electromechanical systems (MEMS) actuator aimed for a DC switch structure using the PiezoMUMPs technology. The chevron actuator employs stacked composite SOI/SiO2/Al–Cr layers. The potential of crosstalk between the switch and DC heater actuator is mitigated. An oxide (SiO2) layer acts as an interface between the thin film aluminum (Al) heater and a silicon (Si) structural layer that forms the MEMS switch for power switching applications. Preliminary results show that the out-of-plane motion of the proposed design is reduced by more than 10× in comparison to a reference design. The average power consumption during actuation was measured to be ~ 80 mW, with a switching speed of < 35 ms. The switch can sustain up to 350 V at its terminals, enabling it for use in high voltage harsh environments.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123286268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Quick Compact Model Development Through Slow Transient Simulation: An Alternative Approach to Table Models for Emerging Nanodevices 通过慢速瞬态模拟快速紧凑模型开发:新兴纳米器件表模型的替代方法
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842125
Maximilian Reuter, Dakyung Lee, David Riehl, K. Hofmann
{"title":"Quick Compact Model Development Through Slow Transient Simulation: An Alternative Approach to Table Models for Emerging Nanodevices","authors":"Maximilian Reuter, Dakyung Lee, David Riehl, K. Hofmann","doi":"10.1109/NEWCAS52662.2022.9842125","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842125","url":null,"abstract":"A transient simulation which proceeds slowly, compared to all dynamic processes, can be designed to generate a multi-dimensional quasistationary dataset. In order to characterize an electrical device/circuit, in this work we explore a simulation design based on frequency-nested cosine functions where before an array of quasistationary voltage sweeps was necessary. We present an example of 3 terminal voltages, each in the range of (–1V, 1V), to demonstrate how to plan granularity of a data set. Then we apply this example setup to a novel semiconductor device. Lastly, we present a method to verify if data from the respective transient simulation can indeed be interpreted as quasistationary data. The proposed methods are described in a generic mathematical way to allow transfer to other dynamic systems incorporating fluidic, mechanic or thermic processes.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114576237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants 一种专用于神经记录脑植入物的10- b330nw三阶预测SAR ADC
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9841982
Mohsen Namavar, R. Lotfi, A. M. Sodagar
{"title":"A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants","authors":"Mohsen Namavar, R. Lotfi, A. M. Sodagar","doi":"10.1109/NEWCAS52662.2022.9841982","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9841982","url":null,"abstract":"This paper reports on a predictive analog-todigital converter (ADC). The proposed ADC employs a linear predictive filter to prepare a prediction for the current sample based on the values of the previous digital codes. This leads to significant reduction in the mean bit cycle of the converter. It is shown in this work that this idea is significantly more effective for the digitization of biological signals (e.g., intra-cortical neural signals). Compared with other similar techniques available in the literature, the proposed predictive ADC is significantly more successful for small signal-to-noise ratios. The proposed algorithm results in 48% and 37% reduction in the converter’s mean bit cycle compared with the conventional and LSB-first structures, respectively. Designed and post-layout simulated in a 90-nm standard CMOS technology and operated at 200 kS/s with a supply voltage of 0.4 V, the 10-bit predictive ADC consumes 330 nW. The circuit occupies a core area of 0.025 mm2, achieves an ENOB of 9.42 bits, a figure-of-merit of 2.4 fJ/conv.-step, and an SFDR of 65.8 dB. The DNL and INL of the circuit are within 0.45 LSB and 0.56 LSB, respectively.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124316104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low complex Hardware Architecture Design Methodology for Cubic Spline Interpolation Technique for Assistive Technologies 辅助技术三次样条插值技术的低复杂硬件体系结构设计方法
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842110
Ganesh Cheduluri, Swati Bhardwaj, G. Naik, Vidhumouli Hansigida, Appa Rao Nali, A. Acharyya
{"title":"Low complex Hardware Architecture Design Methodology for Cubic Spline Interpolation Technique for Assistive Technologies","authors":"Ganesh Cheduluri, Swati Bhardwaj, G. Naik, Vidhumouli Hansigida, Appa Rao Nali, A. Acharyya","doi":"10.1109/NEWCAS52662.2022.9842110","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842110","url":null,"abstract":"The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards Current-Mode Analog Implementation of Deep Neural Network Functions 深度神经网络函数的电流模式模拟实现
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842017
Shihao Wang, K. M. Al-Tamimi, Issam Hammad, K. El-Sankary
{"title":"Towards Current-Mode Analog Implementation of Deep Neural Network Functions","authors":"Shihao Wang, K. M. Al-Tamimi, Issam Hammad, K. El-Sankary","doi":"10.1109/NEWCAS52662.2022.9842017","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842017","url":null,"abstract":"This paper proposes a current-mode analog circuit design that operates in the subthreshold region to implement various Deep Neural Network (DNN) functions. The implemented circuit blocks include binary weight multiplier layer, Rectified Linear Unit (ReLU), and approximate Softmax layer. The proposed designs were implemented using 180nm CMOS technology with a 1.5V power supply. Furthermore, the impact of the proposed design on accuracy was simulated using the MNIST dataset. Using a four layers Convolutional Neural Network (CNN) with an 8 bits resolution, the design achieved an accuracy of 99.02% with 68.21uW power consumption, which is 35.65% lower than the existing analog DNN design.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"55 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120935845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Multilayer Perceptron (MLP) Regressor Network for Monitoring the Depth of Anesthesia 用于麻醉深度监测的多层感知器(MLP)回归网络
2022 20th IEEE Interregional NEWCAS Conference (NEWCAS) Pub Date : 2022-06-19 DOI: 10.1109/NEWCAS52662.2022.9842242
Muhammad Ibrahim Dutt, Wala Saadeh
{"title":"A Multilayer Perceptron (MLP) Regressor Network for Monitoring the Depth of Anesthesia","authors":"Muhammad Ibrahim Dutt, Wala Saadeh","doi":"10.1109/NEWCAS52662.2022.9842242","DOIUrl":"https://doi.org/10.1109/NEWCAS52662.2022.9842242","url":null,"abstract":"Monitoring the depth of anesthesia (DoA) during surgical procedures is very critical for patients’ health. Any inaccurate dosage of the anesthetic agents can result in postoperative health issues or complications such as comma or intraoperative awareness. The accurate estimation of DoA using the electroencephalogram (EEG) signals is still a problem in many DoA monitors. This paper proposes a novel approach for accurate DoA estimation based on Stationary Wavelet Transform (SWT) spectral features while using Multilayer Perceptron (MLP) Regressor Network for the prediction of DoA index. The regressor utilizes an optimized temporal, fractal, and spectral feature set to identify the patient’s conscious level irrespective of age and the type of anesthetic agent. The proposed algorithm is validated on 95 patients (age 5 months-67 years), (weight: 6 - 90 Kg). The anesthetic agents used in this study include Propofol, Sevoflurane, Isoflurane, Fentanyl, Ketamine, and Caudal. The proposed DoA regressor outperforms the state-of-the-art DoA prediction algorithms by predicting highly accurate DoA indexes with an overall Mean Absolute Error (MAE) of 0.014 and Mean Squared Error (MSE) of 0.02 while utilizing minimized feature set and a deep learning-based MLP regression network. The minimized feature set allows efficient implementation on-chip.","PeriodicalId":198335,"journal":{"name":"2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121263759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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