2005 IEEE International Symposium on Circuits and Systems最新文献

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Ultra low voltage design considerations of SOI SRAM memory cells SOI SRAM存储单元的超低电压设计考虑
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465531
O. Thomas, A. Amara
{"title":"Ultra low voltage design considerations of SOI SRAM memory cells","authors":"O. Thomas, A. Amara","doi":"10.1109/ISCAS.2005.1465531","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465531","url":null,"abstract":"This paper introduces a systematic design methodology dedicated to partially depleted SOI (PD-SOI) SRAM memory cells. We have adapted the conventional design methods in order to take into account the secondary effects that are related to the PD-SOI floating body transistor. The method has been applied both to a conventional 6-transistor SRAM cell and a 4-transistor self-refresh cell we have developed. Comparisons based on simulations using a 130 nm PD-SOI technology are presented.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low voltage analog synthesizer of orthogonal signals: a current-mode approach 正交信号的低压模拟合成器:电流模式方法
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465435
V.J.S. Oliveira, N. Oki
{"title":"Low voltage analog synthesizer of orthogonal signals: a current-mode approach","authors":"V.J.S. Oliveira, N. Oki","doi":"10.1109/ISCAS.2005.1465435","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465435","url":null,"abstract":"An analog synthesizer of orthogonal signals for digital CMOS technology and 3V supply voltage is presented. The adaptive architecture accomplishes the synthesis of mutually orthogonal signals, such as trigonometric and polynomial basis. Experimental results using 0.35 /spl mu/m AMS CMOS process are presented for generation of the cosine and Legendre basis.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and implementation of multiplierless adjustable fractional-delay all-pass filters 无乘法器可调分数延迟全通滤波器的设计与实现
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464965
J. Yli-Kaakinen, T. Saramäki
{"title":"Design and implementation of multiplierless adjustable fractional-delay all-pass filters","authors":"J. Yli-Kaakinen, T. Saramäki","doi":"10.1109/ISCAS.2005.1464965","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464965","url":null,"abstract":"This paper describes an algorithm for finding the multiplierless coefficient representations for adjustable fractional-delay (AFD) all-pass filters. The optimization is performed in three basic steps. First, an initial filter is generated using a simple design scheme. Second, this filter is used as a start-up solution for the nonlinear optimization algorithm which is employed for determining a parameter space of the infinite-precision coefficients. This space includes the feasible space where the filter meets the given criteria. The third step involves finding the discrete coefficient values in this space so that the resulting filter meets the criteria with the simplest coefficient representation forms. Examples are included for illustrating the efficiency of the proposed synthesis scheme. In addition, the performance and the complexity of the multiplierless AFD all-pass filters are compared with those of the multiplierless AFD finite-impulse response filters implemented using the modified Farrow structure proposed by Vesma and Saramaki (1997). This comparison shows that the number of adders for the resulting filters are in the best case less than 50 percent compared with those implemented using the modified Farrow structure.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116172335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware accelerator design for video segmentation with multi-modal background modelling 基于多模态背景建模的视频分割硬件加速器设计
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464795
Hongtu Jiang, H. Ardö, V. Öwall
{"title":"Hardware accelerator design for video segmentation with multi-modal background modelling","authors":"Hongtu Jiang, H. Ardö, V. Öwall","doi":"10.1109/ISCAS.2005.1464795","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464795","url":null,"abstract":"Among many of the algorithms for video segmentation, one based on a statistical background model (Stauffer, C. and Grimson, W., Proc. IEEE Conf. Computer Vision and Pattern Recognition, 1999) was developed with the unique feature of robustness in multi-modal background scenarios. However, with a large number of calculations due to the pixel-wise processing of each frame, such an algorithm could only achieve a low frame rate, far from real-time requirements, on computers. A hardware accelerator is proposed, with a dedicated architecture aimed at addressing both computation and memory bandwidth demands. The whole system is targeted to an FPGA platform, which serves as a real-time test bench where long term effects caused by fixed point quantization and various parameter settings can be studied. Meanwhile, memory bandwidth as well as memory size are investigated, and reduction by up to 60 percent, through similarity exploitation for neighboring Gaussian parameters, is envisioned. Furthermore, a controller synthesis tool is used to relieve the effort for the manual design of the complex control unit which schedules the operations of the whole system.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116388614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Field test results for low power bearing estimator sensor nodes 低功率轴承估计器传感器节点的现场测试结果
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465558
P. Julián, A. Andreou, G. Cauwenberghs, M. Stanaćević, David H. Goldberg, P. Mandolesi, Laurence Riddle, S. Shamma
{"title":"Field test results for low power bearing estimator sensor nodes","authors":"P. Julián, A. Andreou, G. Cauwenberghs, M. Stanaćević, David H. Goldberg, P. Mandolesi, Laurence Riddle, S. Shamma","doi":"10.1109/ISCAS.2005.1465558","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465558","url":null,"abstract":"The paper describes experimental results of low power sensor nodes designed to perform bearing estimation. The nodes are intended to form a wireless sensor network able to locate an audio source. Two different nodes are tested: one is based on a cross-correlation derivative integrated circuit (IC), and the other on a gradient flow IC. Implementation details and experimental results of both systems working in a natural environment are presented.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"141 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Generalized sidelobe cancellers with leakage constraints 具有泄漏约束的广义旁瓣对消器
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465443
Yongzhi Liu, Q. Zou, Zhiping Lin
{"title":"Generalized sidelobe cancellers with leakage constraints","authors":"Yongzhi Liu, Q. Zou, Zhiping Lin","doi":"10.1109/ISCAS.2005.1465443","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465443","url":null,"abstract":"A class of linear constraints is proposed for generalized sidelobe cancellers (GSCs) in the presence of direction of arrival (DOA) mismatch. In order to alleviate the signal cancellation problem, the class of linear constraints for the adaptive canceller in a GSC, called leakage constraints, is derived, based on the estimation of blocking matrix leakages. With the leakage constraints, the modified GSC is robust against DOA mismatch. Compared with the well-known adaptive beamformer with derivative constraints, fewer constraints are required and the capability of interference and noise cancellation is improved. Computer simulations demonstrate the effectiveness of the proposed GSC with leakage constraints.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122319581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A novel switched-current phase locked loop 一种新型开关电流锁相环
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465212
P. Wilson, R. Wilcock, B. Al-Hashimi
{"title":"A novel switched-current phase locked loop","authors":"P. Wilson, R. Wilcock, B. Al-Hashimi","doi":"10.1109/ISCAS.2005.1465212","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465212","url":null,"abstract":"The paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2/sup nd/ order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35 /spl mu/m BSim3v3 CMOS models of two PLL designs (10 MHz FSK demodulator, 500 MHz frequency synthesizer) are included.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122324541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Stability analysis of pulse-width-modulated feedback systems with type 2 modulation: the critical case 2型调制脉宽调制反馈系统的稳定性分析:临界情况
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465305
Ling Hou
{"title":"Stability analysis of pulse-width-modulated feedback systems with type 2 modulation: the critical case","authors":"Ling Hou","doi":"10.1109/ISCAS.2005.1465305","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465305","url":null,"abstract":"In this paper, the author presents new Lyapunov and Lagrange stability results for the critical case of pulse-width-modulated (PWM) feedback systems with type 2 modulation. The linear plant considered herein is assumed to be critically stable, i.e., the plant has one and only one pole at the origin and the rest of the poles are in the left half of the complex plane. An algorithm is incorporated to allow easy calculation of the stability bound. The applicability of the present results is demonstrated by means of two specific examples.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122672598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Deterministic and low power BIST based on scan slice overlapping 基于扫描片重叠的确定性低功耗BIST
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465924
Ji Li, Yinhe Han, Xiaowei Li
{"title":"Deterministic and low power BIST based on scan slice overlapping","authors":"Ji Li, Yinhe Han, Xiaowei Li","doi":"10.1109/ISCAS.2005.1465924","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465924","url":null,"abstract":"This paper presents a new deterministic pattern generation structure that can be used in conjunction with any LFSR reseeding scheme. The proposed scheme utilizes scan slice overlapping to reduce the number of specified bits and the number of transitions at the same time. Thus, it can significantly reduce test power and evens control signals. Experimental results indicate that the proposed method significantly reduces the switching activity by 80% and only needs relatively small test data storage.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Multi-user receiver using conjugate gradient method for wideband CDMA 基于共轭梯度法的宽带CDMA多用户接收机
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464599
Y. Takizawa, Cindy Bernadeth Tjitrosoewarno, A. Fukasawa
{"title":"Multi-user receiver using conjugate gradient method for wideband CDMA","authors":"Y. Takizawa, Cindy Bernadeth Tjitrosoewarno, A. Fukasawa","doi":"10.1109/ISCAS.2005.1464599","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464599","url":null,"abstract":"The paper describes a new scheme for a multi-user receiver to improve the capacity of wideband CDMA systems. The scheme is obtained by applying a conjugate gradient method (CGM) based on a mathematical approach. CGM gives an iterative solution of a large-scale matrix under multiple access interference environments. The relation between the transmitted and received signals is represented by a sparse matrix, which has diagonal components almost equal to one and other components approaching 0. This matrix equation is expected to be solved effectively by using CGM. The proposed scheme has been shown to have three times enhancement in capacity compared to single user receiver.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122456713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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