2005 IEEE International Symposium on Circuits and Systems最新文献

Behavioural modeling and simulation of a switched-current phase locked loop 开关电流锁相环的行为建模与仿真

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-10-17 DOI: 10.1109/BMAS.2005.1518183

P. Wilson, R. Wilcock

{"title":"Behavioural modeling and simulation of a switched-current phase locked loop","authors":"P. Wilson, R. Wilcock","doi":"10.1109/BMAS.2005.1518183","DOIUrl":"https://doi.org/10.1109/BMAS.2005.1518183","url":null,"abstract":"Switched-current (SI) methods can provide an effective route to the implementation of analog IC functionality using a standard digital CMOS process. Further, adopting an SI architecture can lead to equivalent performance but with a significantly reduced area compared to switched capacitor structures. The use of behavioural modeling and simulation at a structural and building block level has allowed architectural exploration and evaluation to be carried out on novel topologies based on this approach. The result is an integrated design flow that uses behavioural models to test the performance of the circuit, leading directly to a synthesized structural model that can be verified using a common design platform. This has the obvious benefit of reducing the full custom analog design effort required when developing topologies and building blocks for new processes. We describe the design approach for a phase locked loop (PLL) based on a novel SI architecture using behavioural models written in VHDL-AMS. Simulations demonstrate the performance of the design at a high level and are used to optimize the behaviour of the loop response with regard to design specifications. The modeling approach is explained. The advantage of using behavioural models is highlighted. The resulting simulations are consistent with transistor level simulation results, but several orders of magnitude faster. The resulting design achieves a performance that is comparable with designs using current techniques, but with significantly reduced area.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129527768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient homotopy method for finding DC operating points of nonlinear circuits 一种求非线性电路直流工作点的有效同伦方法

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-07-25 DOI: 10.1093/ietfec/e88-a.10.2554

Y. Imai, K. Yamamura, Y. Inoue

引用次数: 10

A 5GHz to 6GHz integrated differential LNA 5GHz到6GHz的集成差分LNA

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-07-25 DOI: 10.1109/ISCAS.2005.1465710

W. M. Lim, H. Ma, M. Do, K. Yeo

引用次数: 3

A foveated AER imager chip [address event representation] 一种注视点AER成像芯片[地址事件表示]

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-07-25 DOI: 10.1109/ISCAS.2005.1465196

M. Azadmehr, J. Abrahamsen, P. Häfliger

{"title":"A foveated AER imager chip [address event representation]","authors":"M. Azadmehr, J. Abrahamsen, P. Häfliger","doi":"10.1109/ISCAS.2005.1465196","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465196","url":null,"abstract":"We have developed a foveated imager chip with high resolution photo-cells (referred to as static pixels) in the center that are surrounded by more space consuming adaptive change detection pixels (referred to as dynamic pixels). Inspired by the neurons of biological nervous systems, they emit short voltage pulses, the static pixels with a frequency proportional to light intensity, the dynamic pixels whenever they detect a relative change in irradiance. The pulses are transmitted off-chip by the address event representation (AER) protocol, i.e. via a digital bus as the identifying address of the sending pixel. For the motion pixels, this read-out strategy has the advantage of low latency in the order of 100 ns after a change is encountered. (Whereas a scanning read-out strategy would on average suffer a delay of half of the frame scanning period.) Mounted on a pan-tilt system, the peripheral motion detectors could, for instance, be used to steer the imager such that the image of a moving object falls onto the central pixel array where it can then be examined in detail at a higher resolution. Or, if the imager is mounted statically, they can detect an intruder and cause the central pixels to be turned on for more detailed observation","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128719212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Optimal user weighting fusion in DWT domain on-line signature verification DWT域在线签名验证中最优用户权重融合

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-07-20 DOI: 10.1109/ISCAS.2005.1464933

I. Nakanishi, H. Sakamoto, Y. Itoh, Y. Fukui

引用次数: 8

A combined two's complement and floating-point comparator 二进制补码和浮点比较器的组合

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-26 DOI: 10.1109/ISCAS.2005.1464531

J. Stine, M. Schulte

引用次数: 40

Design automation of single-ended LNAs using symbolic analysis 使用符号分析实现单端LNAs的自动化设计

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464832

Gülin Tulunay, S. Balkır

引用次数: 8

On global dynamic behavior of weakly connected cellular nonlinear networks 弱连通元胞非线性网络的全局动力学行为

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465674

M. Gilli, M. Bonnin, F. Corinto

引用次数: 5

A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique 采用电流转向技术的低截止频率近红外心率传感器IC

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465189

Alex K. Y. Wong, K. Pun, Yuan-ting Zhang, K. Hung

引用次数: 2

A direct synthesis method of cascaded continuous-time sigma-delta modulators 级联连续时间σ - δ调制器的直接合成方法

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465903

Ramon Tortosa Navas, J. M. Rosa, Á. Rodríguez-Vázquez, F. Fernández

引用次数: 16