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2005 IEEE International Symposium on Circuits and Systems最新文献

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An area-efficient and protected network interface for processing-in-memory systems 用于内存处理系统的区域高效且受保护的网络接口
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465246
S. Mediratta, C. Steele, J. Sondeen, J. Draper
{"title":"An area-efficient and protected network interface for processing-in-memory systems","authors":"S. Mediratta, C. Steele, J. Sondeen, J. Draper","doi":"10.1109/ISCAS.2005.1465246","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465246","url":null,"abstract":"This paper describes the implementation of an area-efficient and protected user memory-mapped network interface, the pbuf (parcel buffer), for the data intensive architecture (DIVA) processing-in-memory (PIM) system. This implementation of the pbuf in TSMC 0.18 /spl mu/m CMOS technology displays an aggregate bi-directional throughput of 48.08 Gbps, using low area (0.56 mm/sup 2/) and power consumption (32.30 mW). These characteristics, especially the low area and power, have made the current implementation an ideal choice for assimilation in DIVA PIM systems, since low area and power are critical design requirements in the PIM philosophy. The pbuf implementation has been verified by the execution of a 2-PIM transitive closure benchmark at 140 MHz on an HP Itanium2-based Long's Peak server containing DIMMs populated with DIVA-H PIM chips.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121329268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Scheduling design for distributed video-on-demand servers 分布式视频点播服务器调度设计
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464895
Yinqing Zhao, C.-C. Jay Kuo
{"title":"Scheduling design for distributed video-on-demand servers","authors":"Yinqing Zhao, C.-C. Jay Kuo","doi":"10.1109/ISCAS.2005.1464895","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464895","url":null,"abstract":"An online request migration scheme and a dynamic content update strategy for distributed video-on-demand (VoD) systems are proposed in this work to reduce the service failure rate and the server-side network bandwidth consumption. By improving the random early migration (REM) scheme that was designed for a centralized VoD server system, we propose a cost-aware REM (CAREM) scheme to reduce the network bandwidth consumption of the migration in a distributed environment. A dynamic content update strategy is also proposed based on the server-video affinity metric to reconfigure video copies assigned to media servers. Extensive simulations show that CAREM together with the dynamic content update strategy can reduce both the failure rate and the server bandwidth consumption.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121415703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-speed and low-power design of parallel turbo decoder 高速低功耗并联式涡轮解码器设计
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1466011
Zhiyong He, S. Roy, P. Fortier
{"title":"High-speed and low-power design of parallel turbo decoder","authors":"Zhiyong He, S. Roy, P. Fortier","doi":"10.1109/ISCAS.2005.1466011","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1466011","url":null,"abstract":"This paper presents the high speed and low power design of a turbo decoder with parallel architecture. To solve the memory conflict problem of extrinsic information in such parallel architectures, a two-level mapping approach is proposed for designing a collision-free parallel interleaver. Since the warm-up process in the parallel architecture increases the decoding delay, a new parallel architecture without warm-up is proposed for high speed applications. The proposed parallel architecture increases decoding speed by 6-50% for a 16-parallel decoder. To reduce the power consumption of the decoder with parallel architecture, a simple truncation approach is proposed to reduce the storage requirement of the extrinsic information and path metrics without any extra hardware cost. The proposed truncation approach reduces the power consumption with little performance degradation.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Congestion-optimized scheduling of video over wireless ad hoc networks 无线自组织网络上视频的拥塞优化调度
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465391
Eric Setton, Xiaoqing Zhu, B. Girod
{"title":"Congestion-optimized scheduling of video over wireless ad hoc networks","authors":"Eric Setton, Xiaoqing Zhu, B. Girod","doi":"10.1109/ISCAS.2005.1465391","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465391","url":null,"abstract":"We analyze the benefits of information sharing between the application layer and the transport layer, for streaming video encoded at several different qualities, in a mobile wireless network. The application relies on statistics collected at the transport layer and on a video distortion model to select the highest quality that can be supported by the network. At the transport layer, congestion-distortion optimized scheduling is performed to select packets which maximize the received video quality. Experiments performed over a simulated multi-hop wireless network, with H.264 encoded video, show benefits of the proposed approach.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Delay modeling of CMOS/CPL logic circuits CMOS/CPL逻辑电路的延迟建模
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465910
Y. Wan, M. Shams
{"title":"Delay modeling of CMOS/CPL logic circuits","authors":"Y. Wan, M. Shams","doi":"10.1109/ISCAS.2005.1465910","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465910","url":null,"abstract":"Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. The combination of standard CMOS with CPL (complementary pass-transistor logic) is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved and fast algorithms for intra 4/spl times/4 mode decision in H.264/AVC H.264/AVC中4/ sp1次/4模式决策的改进和快速算法
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465040
Chao-Hsuing Tseng, Hung-Ming Wang, J. Yang
{"title":"Improved and fast algorithms for intra 4/spl times/4 mode decision in H.264/AVC","authors":"Chao-Hsuing Tseng, Hung-Ming Wang, J. Yang","doi":"10.1109/ISCAS.2005.1465040","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465040","url":null,"abstract":"In H.264 advanced video coding (AVC), intra prediction plays an important role in the compression of intraframes. H.264 provides two kinds of cost function, sum of absolute difference (SAD) or sum of absolute transform difference (SATD) plus 4P/spl lambda/ (Q/sub p/) by using the Hadamard transform, to decide the best intra mode. We first propose an improved cost function, which uses the sum of absolute integer transform difference (SAITD) and then develop two fast transform algorithms, each for the Hadamard transform used in SATD and the integer transform used in SAITD. These two fast transform algorithms are based on the property of linear transform and spatial relation in the predicted block. With the fast Hadamard transform algorithm, we can reduce the computation nearly by half compared to the original algorithm. With a small increase of computation, the SAITD achieves better coding performance in low bit rate than the SATD.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116264520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Baseball event detection using game-specific feature sets and rules 使用特定于游戏的功能集和规则的棒球事件检测
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465465
C.-H. Liang, W. Chu, J. Kuo, Ja-Ling Wu, Wen-Huang Cheng
{"title":"Baseball event detection using game-specific feature sets and rules","authors":"C.-H. Liang, W. Chu, J. Kuo, Ja-Ling Wu, Wen-Huang Cheng","doi":"10.1109/ISCAS.2005.1465465","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465465","url":null,"abstract":"A framework for scrutinizing baseball videos is proposed. By applying the well-defined baseball rules, this work exactly identifies what happens in a game rather than roughly finding some interesting parts. After extracting the information changes on the superimposed caption, a rule-based decision is applied to detect meaningful events. Only three types of information, including number of outs, number of scores, and base-occupation situation, have to be considered in the detection process. The experimental results show the effectiveness of this framework and demonstrate some research opportunities about generating semantic-level summary or indexing for sports videos.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121490537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Accurate high frequency noise modeling in SiGe HBTs SiGe hbt高频噪声的精确建模
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465261
M. A. Selim, A. Salama
{"title":"Accurate high frequency noise modeling in SiGe HBTs","authors":"M. A. Selim, A. Salama","doi":"10.1109/ISCAS.2005.1465261","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465261","url":null,"abstract":"A new extension to account for correlation between the shot noise sources of SiGe HBTs is formulated. This model is valid to be added to existing compact models. Using this model, circuit level noise parameters, including the minimum noise figure, the optimum generator admittance and the noise resistance, are calculated from noise sources and the small signal y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. The minimum noise figure simulated was found to be less than the original model without correlation ranging from -23% at 2 GHz to -6% at 26 GHz, giving a better fit to measured data.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121530207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders 基于存储器的低密度奇偶校验卷积解码器FPGA实现架构
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464593
S. Bates, Gary L. Block
{"title":"A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders","authors":"S. Bates, Gary L. Block","doi":"10.1109/ISCAS.2005.1464593","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464593","url":null,"abstract":"Low-density parity-check convolutional codes complement their popular block-oriented counterparts and may be more suitable in certain communication applications. These include streaming voice and video and packet switching networks. In this paper we introduce these codes and propose a memory-based decoder architecture that is well suited for implementation on field-programmable gate arrays. We present an overview of the architecture and demonstrate its efficiency over register-based architectures. We then discuss a realization of this architecture that can trade performance for throughput and can achieve up to 120 Mb/s of information throughput and a BER as low as 2 /spl times/ 10/sup -6/ at an Eb/Nq of 3 dB on an Altera Stratix FPGA. For a first-generation implementation this compares favorable with current block-oriented decoder implementations.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121685991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Demosaicing with improved edge direction detection 用改进的边缘方向检测去马赛克
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465020
Xiaomeng Wang, Weisi Lin, P. Xue
{"title":"Demosaicing with improved edge direction detection","authors":"Xiaomeng Wang, Weisi Lin, P. Xue","doi":"10.1109/ISCAS.2005.1465020","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465020","url":null,"abstract":"A new edge adaptive color demosaicing method for Bayer pattern images of single-sensor digital cameras is presented in this paper. An edge direction detector for narrow edges is proposed by making full use of inter-channel correlation to determine edge directions within the smallest detection radius. A combinative criterion is then formulated to cater for the diversity of edge occurrence in real-world scenes. The improvement of the proposed demosaicing scheme is achieved by an effective detection on edge directions, emphasizing on green channel restoration and the overall refinement. Experimental results show that the new scheme preserves better edge details, reduces color aliasing artifacts, and achieves both higher signal fidelity and higher visual image quality as compared with some existing schemes.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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