Delay modeling of CMOS/CPL logic circuits

Abstract

Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. The combination of standard CMOS with CPL (complementary pass-transistor logic) is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain's propagation time and drive capability.