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2005 IEEE International Symposium on Circuits and Systems最新文献

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A study on distribution network planning with considering customer's utilization of distributed generators 考虑用户对分布式发电机的利用的配电网规划研究
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465689
K. Koeda, H. Sasaki, Teppei Ueyama, Y. Zoka, N. Yorino
{"title":"A study on distribution network planning with considering customer's utilization of distributed generators","authors":"K. Koeda, H. Sasaki, Teppei Ueyama, Y. Zoka, N. Yorino","doi":"10.1109/ISCAS.2005.1465689","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465689","url":null,"abstract":"The paper proposes a new framework for distribution network planning, in order to obtain the maximum merit of utilities and customers under the condition of mass installed distributed generators (DGs). An objective function, which includes an ancillary service charge for cogeneration systems, is formulated to obtain maximum profits for customers, and the authors discuss the reduction of a customer's energy costs for installation of DGs. On the other hand, an objective function, which includes an ancillary service charge for distribution network planning, is formulated to obtain maximum profits for utilities, and the authors discuss reduction of the utilities' investment cost and distribution system loss for the installation of DGs. The authors also discuss the ancillary service rate under the consideration of cost effects for utilities and customers. The advantage of the proposed method is demonstrated through several numerical simulations by using example distribution systems.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Designing and packaging technology of Renesas SIP 瑞萨电子SIP的设计与封装技术
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465988
N. Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, T. Akazawa
{"title":"Designing and packaging technology of Renesas SIP","authors":"N. Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, T. Akazawa","doi":"10.1109/ISCAS.2005.1465988","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465988","url":null,"abstract":"Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMA 基于遗传算法的MC-CDMA联合频偏估计和多用户检测
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1093/ietcom/e88-b.11.4386
Hoang-Yang Lu, Wen-Hsien Fang
{"title":"Joint frequency offset estimation and multiuser detection using genetic algorithm in MC-CDMA","authors":"Hoang-Yang Lu, Wen-Hsien Fang","doi":"10.1093/ietcom/e88-b.11.4386","DOIUrl":"https://doi.org/10.1093/ietcom/e88-b.11.4386","url":null,"abstract":"In order to combat intercarrier interference (ICI) and multiple access interference (MAI) simultaneously to achieve reliable performance in multi-carrier code division multiple access (MC-CDMA) systems, the paper proposes a new scheme for joint frequency offset estimation and multiuser symbol detection. The new approach is based on the widespread maximum likelihood principle to carry out concurrently frequency offset estimation to alleviate the ICI and multiuser detection to mitigate the MAI. The joint decision statistic, however, is highly nonlinear and conventional linear schemes are not applicable. To reduce the computational complexity without an increase of additional mechanisms, we employ a genetic algorithm (GA) to solve the nonlinear optimization involved. Due to the robustness of the GA, the joint decision statistic can be efficiently solved and near optimum results can be obtained. Simulation results show that the proposed approach offers satisfactory performance in various scenarios.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123925472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An embedded processor based SOC test platform 基于嵌入式处理器的SOC测试平台
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465254
Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong
{"title":"An embedded processor based SOC test platform","authors":"Kuen-Jong Lee, Chia-Yi Chu, Yu-Ting Hong","doi":"10.1109/ISCAS.2005.1465254","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465254","url":null,"abstract":"In this paper, we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated test access mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Evaluating a blind channel estimation technique that uses a hardware efficient equalizer 评估一种使用硬件高效均衡器的盲信道估计技术
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465936
Y. Ye, S. Abeysekera
{"title":"Evaluating a blind channel estimation technique that uses a hardware efficient equalizer","authors":"Y. Ye, S. Abeysekera","doi":"10.1109/ISCAS.2005.1465936","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465936","url":null,"abstract":"The blind parameter estimation of a non-minimum phase (NMP) channel having a finite impulse response (FIR) is studied. An efficient and reliable blind estimation algorithm is proposed which is based on a combination of second order statistics (SOS) and the kurtosis of the signals. SOS based methods provide efficient estimation of channel zeros from a very small number of samples. As the SOS based methods are phase blind, the kurtosis is used to resolve the ambiguity in system zero locations. It is also shown that the equalizer output could be exploited recursively to improve the estimation accuracy using finite alphabet (FA) properties. It is noted that, as all the available information for blind channel parameter estimation is used, the proposed method can achieve a very high accuracy. Performance of the estimation method is also discussed.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"29 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packet scheduling based on Geo/sup Y//G//spl infin/ input process modeling for streaming video 基于Geo/sup / Y/ G//spl infin/ input过程建模的流视频分组调度
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465323
Sujeong Choi, S. Kang, Bara Kim
{"title":"Packet scheduling based on Geo/sup Y//G//spl infin/ input process modeling for streaming video","authors":"Sujeong Choi, S. Kang, Bara Kim","doi":"10.1109/ISCAS.2005.1465323","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465323","url":null,"abstract":"We introduce a new stochastic process called Geo/sup Y//G//spl infin/ input process with beta-distributed batch size and Weibull-like autocorrelation function in order to model video traffic. Investigating the overflow probability of a queueing system by large deviation theory, we develop a streaming scheduling algorithm by applying the overflow analysis result to estimating the packet deadline-missing probability. Through experiments with 30-minute long movie traces, we show that our proposed scheduling scheme outperforms existing schemes based on fractional Brownian motion and Markovian models.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123646991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and formal verification of dataflow graph in system-level design using Petri net 系统级设计中数据流图的Petri网建模与形式化验证
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465925
Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung
{"title":"Modeling and formal verification of dataflow graph in system-level design using Petri net","authors":"Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung","doi":"10.1109/ISCAS.2005.1465925","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465925","url":null,"abstract":"Formal verification at system-level, which also means architecture verification, is different from functional verification at RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping onto silicon. However, a suitable CAD tool is absent to support the simulation and verification at high-level. This paper presents a novel modeling and high-level verification methodology based on a Petri net (PN) model. By the proposed method, a DSP algorithm system in the form of FSFG (fully specified flow graph) is transformed into a PN model. Moreover, verification methods which include static and dynamical phases are applied in the PN domain. Finally, we introduce our software implementation, called HiVED, to show the experimental results.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems 嵌入式和内存处理系统中浮点单元实现的设计权衡
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465341
Taek-Jun Kwon, J. Sondeen, J. Draper
{"title":"Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems","authors":"Taek-Jun Kwon, J. Sondeen, J. Draper","doi":"10.1109/ISCAS.2005.1465341","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465341","url":null,"abstract":"Hardware support for floating-point (FP) arithmetic is a mandatory feature of modern microprocessor design. There are many alternatives in floating-point unit (FPU) design, and overall performance can be greatly affected by the organization of a floating-point unit. In this paper, design considerations and trade-off factors are evaluated for two types of floating-point unit architecture and implementation optimized under different design goals. The implementation results of the proposed FPUs based on standard cell methodology in TSMC 0.18 /spl mu/m technology exhibit that both designs are well optimized for their target applications. A single-instruction issue design is implemented in very small area; however, a design capable of concurrently executing FP add and multiply instructions is achievable with only a modest 24% area increase.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"4 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique 基于专用功率建模技术的高级DSP架构的电路级功率效率研究
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465823
M. Olivieri, M. Scarana, S. Smorfa
{"title":"Circuit-level power efficiency investigation of advanced DSP architectures based on a specialized power modeling technique","authors":"M. Olivieri, M. Scarana, S. Smorfa","doi":"10.1109/ISCAS.2005.1465823","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465823","url":null,"abstract":"This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121201449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A class of novel blind source extraction algorithms based on a linear predictor 一类新的基于线性预测器的盲源提取算法
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465408
W. Liu, D. Mandic, A. Cichocki
{"title":"A class of novel blind source extraction algorithms based on a linear predictor","authors":"W. Liu, D. Mandic, A. Cichocki","doi":"10.1109/ISCAS.2005.1465408","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465408","url":null,"abstract":"A rigorous analysis of the performance of a blind source extraction structure based on a linear predictor is provided. It is shown that by minimising the mean square prediction error, it is only possible to reach a solution subject to an arbitrary orthogonal transformation, in a manner similar to the principal component analysis. To remove this uncertainty, we propose a new cost function which caters for the ambiguous power levels of the source signals. A novel adaptive blind source extraction algorithm is derived and an alternative method with prewhitening is also introduced. Simulation results verify the proposed algorithms.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121298874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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