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2005 IEEE International Symposium on Circuits and Systems最新文献

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Enhancing vocoder performance for music signals 增强音乐信号的声码器性能
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465520
Visar Berisha, A. Spanias
{"title":"Enhancing vocoder performance for music signals","authors":"Visar Berisha, A. Spanias","doi":"10.1109/ISCAS.2005.1465520","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465520","url":null,"abstract":"Low bit rate standards involving the code excited linear predictive coder (CELP) are typically optimized for telephone speech. The performance of CELP with non-speech signals, and particularly with music, degrades considerably. It is of interest these days to improve the robustness of these coders by adding pre- and post-processing stages to the core compression algorithm. In this paper, we propose a frequency-domain technique involving time-varying filters to enhance the audio quality with a small number of overhead information bits. Preliminary results have shown both qualitative and quantitative improvements in the sound quality.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"537 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Directional interpolation for field-sequential stereoscopic video 场序立体视频的方向插值
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465228
Hsien-Huang P. Wu, M. Sheu, Tungsheng Yang
{"title":"Directional interpolation for field-sequential stereoscopic video","authors":"Hsien-Huang P. Wu, M. Sheu, Tungsheng Yang","doi":"10.1109/ISCAS.2005.1465228","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465228","url":null,"abstract":"Catadioptric stereo systems, which utilize proper combinations of mirrors and lenses, can be designed to capture stereoscopic video using only one camera. The left and right images are usually multiplexed to generate an interlaced video with each image corresponding to one field. This field-sequential format unavoidably reduces the vertical resolution of the image pair by half. We propose a notion called stereoscopic demultiplexing (SD) to recover the original resolution of the image pairs from the field-sequential video. In order to increase the sharpness of the image and avoid jagged artifacts, interpolation along the edge direction is emphasized and a new edge adaptive interpolation (EAI) approach is proposed. Since resolution of the display technology is higher and better than that of the current catadioptric stereo systems, we believe that further improvement on resolution of the acquisition device by software is necessary to make 3D applications become more economical and popular.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130358997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On performance of a charging/rewarding scheme in mobile ad-hoc networks 移动自组织网络中收费/奖励方案的性能研究
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465249
K. Nakano, R. Panta, M. Sengoku, S. Shinoda
{"title":"On performance of a charging/rewarding scheme in mobile ad-hoc networks","authors":"K. Nakano, R. Panta, M. Sengoku, S. Shinoda","doi":"10.1109/ISCAS.2005.1465249","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465249","url":null,"abstract":"In an ad-hoc network, some nodes relay more communications than others. Since relaying is resource consuming, unfairness in terms of the number of communications relayed by different nodes is not desirable. This paper discusses a simple charging/rewarding scheme as a method to reduce the unfairness in the network. We explain the reason why such a scheme works well in a mobile network but does not work well in a static network and discuss some methods to improve performance in the static network.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parametric model order reduction technique for design optimization 设计优化的参数化模型降阶技术
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464831
A. Leung, R. Khazaka
{"title":"Parametric model order reduction technique for design optimization","authors":"A. Leung, R. Khazaka","doi":"10.1109/ISCAS.2005.1464831","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464831","url":null,"abstract":"Model order reduction has proven to be an effective tool for dealing with the computational complexity that arises during the simulation of large interconnect networks. However, in the case of parametric reduced order models, the effectiveness of traditional reduction methods is dependent on the number of moments and cross moments required to construct the orthonormal basis used in the congruence transformation. This can result in a relatively large reduced system in cases when the number of parameters is large. We propose a new approach for constructing the orthonormal basis that is not directly dependent on the moments. This new technique reduces a circuit with respect to many parameters by using singular value decomposition as a tool to filter out redundant information from the original subspaces. The result is a parametric reduced order model that is smaller, but still conserves the essential behavior of the original circuit as a function of frequency and other circuit parameters.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Enriching an analog platform for analog-to-digital converter design 丰富了模数转换器设计的模拟平台
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464830
F. Bernardinis, P. Nuzzo, P. Terreni, A. Sangiovanni-Vincentelli
{"title":"Enriching an analog platform for analog-to-digital converter design","authors":"F. Bernardinis, P. Nuzzo, P. Terreni, A. Sangiovanni-Vincentelli","doi":"10.1109/ISCAS.2005.1464830","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464830","url":null,"abstract":"Platform-based analog design is used to design an analog-to-digital converter reducing power consumption by 26%. This result was achieved by enriching the library of analog components used as the basis of the design with a telescopic operational transconductance amplifier (OTA). We present the way in which the models for this new component necessary to use platform based design can be added quickly and efficiently with the use of analog constraint graphs.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126678701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Soft fault test and diagnosis for analog circuits 模拟电路的软故障测试与诊断
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465055
Peng Wang, Shiyuan Yang
{"title":"Soft fault test and diagnosis for analog circuits","authors":"Peng Wang, Shiyuan Yang","doi":"10.1109/ISCAS.2005.1465055","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465055","url":null,"abstract":"A new SBT diagnosis approach for dealing with soft faults for analog circuits is presented in this paper. A serial of new fault models for analog components are provided and a numerical method which can be easily implemented replaces circuit analysis to obtain the fault models before test. Tolerance issues and multifault diagnosis are also discussed in this paper.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126994370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC 用于CMOS成像仪列级单斜率ADC的1.8 V 3.2 /spl mu/W比较器
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1466047
M. Snoeij, A. Theuwissen, J. Huijsing
{"title":"A 1.8 V 3.2 /spl mu/W comparator for use in a CMOS imager column-level single-slope ADC","authors":"M. Snoeij, A. Theuwissen, J. Huijsing","doi":"10.1109/ISCAS.2005.1466047","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1466047","url":null,"abstract":"In this paper, a 1.8 V 3.2 /spl mu/W comparator is presented. It features a hybrid offset compensation scheme and achieves over 60 dB gain with an input offset below 150 /spl mu/V. The comparator is designed in a 0.18 /spl mu/m CMOS process and is specifically designed to be used as the key component of a column-level single-slope ADC of a CMOS imager. This ADC architecture is attractive because of its low noise, but so far this has come at the price of a relatively high power consumption. Using this comparator design, the power consumption of column-level single-slope ADC can be reduced significantly.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127002115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs 高密度dram中邻域模式敏感故障检测的并行可测试设计
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465970
Ju Yeob Kim, S. Hong, Jong Kim
{"title":"Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs","authors":"Ju Yeob Kim, S. Hong, Jong Kim","doi":"10.1109/ISCAS.2005.1465970","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465970","url":null,"abstract":"The number of test patterns for DRAM increases at least linearly as the memory density increases. It affects the increase in the total cost of memory test. We consider only neighborhood pattern sensitive faults, which are the major and complicated faults in a high density DRAM. Thus, for a 1 G DRAM, the testing time may be several hours if test patterns are applied to memory cells one by one. In order to speed up the testing of high density DRAMs, we propose a parallel accessible decoder, which allows multiple read/write operations at a time. With this scheme, we can reduce the testing time roughly 500 times. This new decoder requires only 8 extra transistors per bit line.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127011767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low energy asynchronous architectures 低能耗异步架构
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465816
Ilya Obridko, R. Ginosar
{"title":"Low energy asynchronous architectures","authors":"Ilya Obridko, R. Ginosar","doi":"10.1109/ISCAS.2005.1465816","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465816","url":null,"abstract":"Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and delay tolerance is the principal design goal, and where performance is not a critical requirement. Three existing adder circuits are studied - two dynamic and one based on pass-transistor logic. All adders combine dual-rail and bundled-data circuits. The circuits are simulated at a wide supply-voltage range, down to their minimal operating point. Leakage energy (at 0.18 /spl mu/m) is found negligible. Transistor count is found to be an unreliable predictor of energy dissipation. A set of the energy minimization rules is defined and two novel adders are proposed, based on these rules - a dynamic circuit and a pass-transistor logic adder. The new adders consume less energy and achieve better performance, confirming the proposed concepts.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An image compression scheme based on parametric Haar-like transform 一种基于参数类哈尔变换的图像压缩方案
2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465030
S. Minasyan, J. Astola, D. Guevorkian
{"title":"An image compression scheme based on parametric Haar-like transform","authors":"S. Minasyan, J. Astola, D. Guevorkian","doi":"10.1109/ISCAS.2005.1465030","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465030","url":null,"abstract":"A new image compression scheme is presented, based on a fast orthogonal parametrically adaptive Haar-like transform, which is a discrete orthogonal transform such that it may be computed with a fast algorithm in structure similar to the classical fast Haar transform, and such that its matrix contains one or more predefined row(s) of an arbitrary order. The nature of the proposed image compression scheme is such that its performance (in terms of PSNR versus compression ratio) cannot be worse than that of the classical DCT (discrete cosine transform) based scheme. Simulations show that a significant performance improvement can be achieved for certain types of images such as medical X-ray images.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130607156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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