Modeling and formal verification of dataflow graph in system-level design using Petri net

Abstract

Formal verification at system-level, which also means architecture verification, is different from functional verification at RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping onto silicon. However, a suitable CAD tool is absent to support the simulation and verification at high-level. This paper presents a novel modeling and high-level verification methodology based on a Petri net (PN) model. By the proposed method, a DSP algorithm system in the form of FSFG (fully specified flow graph) is transformed into a PN model. Moreover, verification methods which include static and dynamical phases are applied in the PN domain. Finally, we introduce our software implementation, called HiVED, to show the experimental results.