N. Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, T. Akazawa
{"title":"瑞萨电子SIP的设计与封装技术","authors":"N. Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, T. Akazawa","doi":"10.1109/ISCAS.2005.1465988","DOIUrl":null,"url":null,"abstract":"Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Designing and packaging technology of Renesas SIP\",\"authors\":\"N. Sakamoto, Norihiko Sugita, Takafumi Kikuchi, Hideki Tanaka, T. Akazawa\",\"doi\":\"10.1109/ISCAS.2005.1465988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.\",\"PeriodicalId\":191200,\"journal\":{\"name\":\"2005 IEEE International Symposium on Circuits and Systems\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2005.1465988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2005.1465988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Renesas Technology Corp. started an SIP (solution integrated product) Project in April 1999, aiming at the promotion of the SiP (system in package) business. SiP can achieve 1/10-1/6 design TAT (turn around time) in comparison with SoC (system on chip). SiP, which packs a few chips in a single package, has also advantages of EMI noise reduction and customer's substrate area reduction by using signal integrity analysis technology and packaging technology of a planar and a stack structure. On the basis of these technologies, we can enlarge SIP for the digital consumer field, analog included digital field, and other fields.
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