2005 IEEE International Symposium on Circuits and Systems最新文献_第6页

Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters 精确和封闭形式的SPICE兼容的无源宏模型与频率相关的参数分布互连

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465949

N. Nakhla, R. Achar, M. Nakhla

引用次数: 0

Learning and recalling of phase pattern in coupled BVP oscillators 耦合BVP振荡器相图的学习与记忆

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465218

Takashi Yamamoto, K. Amemiya, Takashi Yamaguchi

引用次数: 0

An analog modulator/demodulator using a programmable arbitrary waveform generator 一种使用可编程任意波形发生器的模拟调制器/解调器

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1466033

R. Chawla, C. Twigg, P. Hasler

引用次数: 11

Various implementations of topographic, sensory, cellular wave computers 各种实现的地形，感官，蜂窝波计算机

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465957

Á. Zarándy, P. Földesy, P. Szolgay, S. Tõkés, C. Rekeczky, T. Roska

引用次数: 16

A novel approach to the exact design of first- and second-order Bode-type variable-amplitude bilinear-LDI switched-capacitor equalizers 一阶和二阶波德型变幅双线性ldi开关电容均衡器精确设计的新方法

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465616

B. Nowrouzian, A. Fuller, M. Swamy

{"title":"A novel approach to the exact design of first- and second-order Bode-type variable-amplitude bilinear-LDI switched-capacitor equalizers","authors":"B. Nowrouzian, A. Fuller, M. Swamy","doi":"10.1109/ISCAS.2005.1465616","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1465616","url":null,"abstract":"This paper presents a novel approach to the exact design of first- and second-order Bode-type variable-amplitude (VA) bilinear-LDI switched-capacitor (SC) equalizers. The proposed design approach is based on the realization of the VA equalizer transfer function as the transfer function of a frequency-independent two-terminal-pair SC network at its input terminal-pair when its output terminal-pair is terminated in a (frequency-dependent) SC one-terminal-pair realization of the dual of the equalizer shaping impedance function. The resulting first-order equalizers produce fan-shaped lowpass or highpass magnitude-frequency responses, while the resulting second-order equalizer produces a bump-shaped (bandpass) magnitude-frequency response. The salient feature of the proposed SC equalizers is that only a single variable capacitor is required to control the fan amplitude in the first-order equalizers and the bump amplitude in the second-order equalizer. Moreover, these equalizers remain BIBO stable for all possible values of the variable capacitor. In addition, they exhibit the important practical feature that a geometrically symmetric change in the value of the variable capacitor causes a corresponding arithmetically symmetric change in the logarithmic magnitude-frequency response of the VA equalizer. An application example is given to illustrate the main results.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121912038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An all-digital data recovery circuit optimization using Matlab/Simulink 利用Matlab/Simulink对全数字数据恢复电路进行优化

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465628

S. I. Ahmed, T. Kwasniewski

引用次数: 8

A phase-detect synchronous mirror delay for clock skew-compensation circuits 用于时钟偏斜补偿电路的相位检测同步镜像延迟

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464777

Kuo-Hsing Cheng, Chen-Lung Wu, Y. Lo, Chia-Wei Su

{"title":"A phase-detect synchronous mirror delay for clock skew-compensation circuits","authors":"Kuo-Hsing Cheng, Chen-Lung Wu, Y. Lo, Chia-Wei Su","doi":"10.1109/ISCAS.2005.1464777","DOIUrl":"https://doi.org/10.1109/ISCAS.2005.1464777","url":null,"abstract":"A new phase-detect synchronous mirror delay (PSMD) circuit is proposed. The PSMD circuit not only can be operated in the narrow pulse clock signal but also can accept the 50% duty-cycle clocks. The conventional SMD can be locked in 2 clock cycle time, but it just can accept only the narrow pulse clock signal. In this proposed PSMD, we have developed a new mirror delay circuit (MCC) which is composed of a phase detector (PD). Such a new MCC can provide the proposed PSMD to operate in not only the narrow pulse clock signal, but also 50% duty-cycle clocks, and locked in 2 clock cycle time. The HSPICE simulation results are based on TSMC 0.18 /spl mu/m 1P6M N-well CMOS process. The simulation results show that the proposed PSMD can be operated from 200MHz to 400MHz and the static phase error is less than 58.7ps. When the input clock frequency is 200MHz and 400MHz, the power dissipation are 6.03mW and 9.87mW, respectively. In addition, the PSMD operation frequency range is dependent on the number of delay cells, input buffer and clock drive, the principle can be a template in designing the issue of frequency tuning range in SMD.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122119100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Directional watermarks in images 图像中的方向水印

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465506

H. Chao, Cheng-Lun Tai, Yuan-Peir Chen

引用次数: 0

Moore test using Gray code 摩尔测试使用格雷代码

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1465209

T. Hisakado, K. Okumura

引用次数: 1

On the theory and design of a class of PR causal-stable IIR non-uniform recombination cosine modulated filter banks 一类PR -因果稳定IIR非均匀复合余弦调制滤波器组的理论与设计

2005 IEEE International Symposium on Circuits and Systems Pub Date : 2005-05-23 DOI: 10.1109/ISCAS.2005.1464783

S. Chan, S. Yin

引用次数: 3