{"title":"一种新型开关电流锁相环","authors":"P. Wilson, R. Wilcock, B. Al-Hashimi","doi":"10.1109/ISCAS.2005.1465212","DOIUrl":null,"url":null,"abstract":"The paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2/sup nd/ order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35 /spl mu/m BSim3v3 CMOS models of two PLL designs (10 MHz FSK demodulator, 500 MHz frequency synthesizer) are included.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A novel switched-current phase locked loop\",\"authors\":\"P. Wilson, R. Wilcock, B. Al-Hashimi\",\"doi\":\"10.1109/ISCAS.2005.1465212\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2/sup nd/ order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35 /spl mu/m BSim3v3 CMOS models of two PLL designs (10 MHz FSK demodulator, 500 MHz frequency synthesizer) are included.\",\"PeriodicalId\":191200,\"journal\":{\"name\":\"2005 IEEE International Symposium on Circuits and Systems\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2005.1465212\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2005.1465212","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper investigates the design of phase locked loops (PLLs) using the switched current (SI) technique and proposes a novel 2/sup nd/ order PLL architecture that does not require an explicit phase detector, unlike conventional PLL circuits. Simulated results based on 0.35 /spl mu/m BSim3v3 CMOS models of two PLL designs (10 MHz FSK demodulator, 500 MHz frequency synthesizer) are included.
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