2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献_第2页

An SVM-based Hardware Accelerator for Onboard Classification of Hyperspectral Images 基于svm的机载高光谱图像分类硬件加速器

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339869

Lucas A. Martins, Guilherme A. M. Sborz, Felipe Viel, C. Zeferino

{"title":"An SVM-based Hardware Accelerator for Onboard Classification of Hyperspectral Images","authors":"Lucas A. Martins, Guilherme A. M. Sborz, Felipe Viel, C. Zeferino","doi":"10.1145/3338852.3339869","DOIUrl":"https://doi.org/10.1145/3338852.3339869","url":null,"abstract":"Hyperspectral images (HSIs) have been used in civil and military scenarios for ground recognition, urban development management, rare minerals identification, and diverse other purposes. However, HSIs have a significant volume of information and require high computational power, especially for real-time processing in embedded applications, as in onboard computers in satellites. These issues have driven the development of hardware-based solutions able to provide the processing power necessary to meet such requirements. In this paper, we present a hardware accelerator to enhance the performance of one of the most computational expensive stages of HSI processing: the classification. We have employed the Entropy Multiple Correlation Ratio procedure to select the spectral bands to be used in the training process. For the classification step, we have applied a Support Vector Machine classifier with a Hamming Distance decision approach. The proposed custom processor was implemented in FPGA and compared with high-level implementations. The results obtained demonstrate that the processor has a silicon cost lower than similar solutions and can perform a realtime pixel classification in 0.1 ms and achieves a state-of-the-art accuracy of 99.7%.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124325273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

CMOS Analog Four-Quadrant Multiplier Free of Voltage Reference Generators CMOS模拟四象限乘法器无电压基准发生器

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339870

Antonio José Sobrinho de Sousa, F. Andrade, Hildeloi dos Santos, Gabriele Costa Goncalves, M. D. Pereira, E. Santana, A. Cunha

引用次数: 2

DNAr-Logic: A constructive DNA logic circuit design library in R language for Molecular Computing DNA - logic:一个基于R语言的DNA逻辑电路设计库

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339854

Renan A. Marks, Daniel K. S. Vieira, Marcos V. Guterres, Poliana A. C. Oliveira, O. V. Neto

引用次数: 3

An Adaptive Discrete Particle Swarm Optimization for Mapping Real-Time Applications onto Network-on-a-Chip based MPSoCs 一种将实时应用映射到基于片上网络的mpsoc的自适应离散粒子群优化

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339835

J. B. D. Barros, R. C. Sampaio, C. Llanos

引用次数: 5

A sub-1mA Highly Linear Inductorless Wideband LNA with Low IP3 sensitivity to Variability for IoT Applications 一种亚1ma的高线性无电感宽带LNA，对物联网应用的可变性具有低IP3灵敏度

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339858

A. L. T. Costa, H. Klimach, S. Bampi

{"title":"A sub-1mA Highly Linear Inductorless Wideband LNA with Low IP3 sensitivity to Variability for IoT Applications","authors":"A. L. T. Costa, H. Klimach, S. Bampi","doi":"10.1145/3338852.3339858","DOIUrl":"https://doi.org/10.1145/3338852.3339858","url":null,"abstract":"This paper proposes a wideband 0.4-2 GHz cascode common-gate LNA that can be used as a building block for a noise canceling topology (which entails its noise to be canceled at the output node). The design strategy is to set the operating point by analyzing the third order coefficient $(alpha_{3})$ of the output current and the output voltage, which is designed using a load composed by a diode-connected PMOS transistor and a resistor in parallel. This operating point allows a reasonable $V_{GS}$ spread, maintaining a high IIP3 which implies a low IIP3 sensitivity to process variability. The design strategy also achieves a current consumption under 1 mA and, depending on the technology node $V_{DD}$ (CMOS 130 nm in this case), it can consume under 1 mW of power. This makes the wideband LNA suitable for IoT applications. Monte Carlo simulations have been carried out to demonstrate the operating region sensitivity to variability and achieves a result of worst case $IIP3_{mu}=+0.2 mathrm{dBm}$ with $sigma=0.8 mathrm{dBm}$ (@2GHz) up to a nominal 2.75 dBm @900 MHz, $S_{11} < -23 mathrm{dB}, mathrm{NF} < 5.5 mathrm{dB}$ (canceled by virtue of its topology), a voltage gain of 11.6-14.6 dB ($S_{21}=6.4-9.4 mathrm{dB}$ with a buffer to $50 Omega$), and consuming just 1.19 mW from a 1.2 V supply.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An FPGA-Based Evaluation Platform for Energy Harvesting Embedded Systems 基于fpga的能量采集嵌入式系统评估平台

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339863

Roberto Paulo Dias Alcantara Filho, O. A. D. L. Junior, C. Júnior

引用次数: 2

Approximate Interpolation Filters for the Fractional Motion Estimation in HEVC Encoders and their VLSI Design HEVC编码器中分数运动估计的近似插值滤波器及其VLSI设计

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339859

Rafael da Silva, Ícaro Siqueira, M. Grellert

{"title":"Approximate Interpolation Filters for the Fractional Motion Estimation in HEVC Encoders and their VLSI Design","authors":"Rafael da Silva, Ícaro Siqueira, M. Grellert","doi":"10.1145/3338852.3339859","DOIUrl":"https://doi.org/10.1145/3338852.3339859","url":null,"abstract":"Motion Estimation (ME) is one of the most complex HEVC steps, consuming more than 60% of the average encoding time, most of which is spent on its fractional part (Fractional Motion Estimation - FME), in which sub-pixel samples are interpolated and searched over to find motion vectors with higher precision. This paper presents hardware designs for the sub-pixel interpolation unit of the FME step. The designs employ approximate computing techniques by reducing the number of taps in each filter to reduce memory access and hardware cost. The approximate filters were implemented in the HEVC reference software to assess their impact on coding performance. A complete interpolation architecture was implemented in VHDL and synthesized with different filter precision and input sizes in order to assess the effect of these parameters on hardware area and performance. The approximate designs reduce the number of adders/subtractors by up to 67.65% and memory bandwidth by up to 75% with a tolerable loss in coding performance (less than 1% using the Bjontegaard Delta bitrate metric). When synthesized to an FPGA device, 52.9% less logic elements are required with a modest increase in frequency.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121031160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Performance Evaluation of HEVC RCL Applications Mapped onto NoC-Based Embedded Platforms 基于noc的嵌入式平台上HEVC RCL应用的性能评价

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339868

Wagner Penny, D. Palomino, M. Porto, B. Zatt, L. Indrusiak

{"title":"Performance Evaluation of HEVC RCL Applications Mapped onto NoC-Based Embedded Platforms","authors":"Wagner Penny, D. Palomino, M. Porto, B. Zatt, L. Indrusiak","doi":"10.1145/3338852.3339868","DOIUrl":"https://doi.org/10.1145/3338852.3339868","url":null,"abstract":"Today, several applications running into embedded systems have to fulfill soft or hard timing constraints. Video applications, like the modern High Efficiency Video Coding (HEVC), e.g., most often have soft real-time constraints. However, in specific scenarios, such as in robotic surgeries, the coupling of satellites and so on, harder timing constraints arise, becoming a huge challenge. Although the implementation of such applications in Networks-on-Chip (NoCs) being an alternative to reduce their algorithmic complexity and meet real-time constraints, a performance evaluation of the mapped NoC and the schedulability analysis for a given application are mandatory. In this work we make a performance evaluation of HEVC Residual Coding Loop (RCL) mapped onto a NoC-based embedded platform, considering the encoding of a single $1920mathrm{x}1080$ pixels frame. A set of analysis exploring the combination of different NoC sizes and task mapping strategies were performed, showing for the typical and upper-bound workload cases scenarios when the application is schedulable and meets the real-time constraints.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reduction of Neural Network Circuits by Constant and Nearly Constant Signal Propagation 恒和近恒信号传播的神经网络电路约简

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339874

A. Berndt, A. Mishchenko, P. Butzen, A. Reis

引用次数: 1

Toward Nanometric Scale Integration: An Automatic Routing Approach for NML Circuits 迈向纳米级集成:NML电路的自动布线方法

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339862

P. A. Silva, O. P. V. Neto, J. Nacif

引用次数: 2