2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)最新文献

Exploiting Approximate Computing for Low-Cost Fault Tolerant Architectures 利用近似计算实现低成本容错架构

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339875

G. Rodrigues, J. Fonseca, F. Benevenuti, F. Kastensmidt, A. Bosio

引用次数: 13

Comparison between Direct and Indirect Learnings for the Digital Pre-distortion of Concurrent Dual-band Power Amplifiers 并行双频功率放大器数字预失真直接学习与间接学习的比较

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339842

Luis Schuartz, Artur T. Hara, A. Mariano, B. Leite, E. G. Lima

{"title":"Comparison between Direct and Indirect Learnings for the Digital Pre-distortion of Concurrent Dual-band Power Amplifiers","authors":"Luis Schuartz, Artur T. Hara, A. Mariano, B. Leite, E. G. Lima","doi":"10.1145/3338852.3339842","DOIUrl":"https://doi.org/10.1145/3338852.3339842","url":null,"abstract":"Current radio-communication systems demand high linearity and high efficiency. The digital baseband pre-distorter (DPD) is a cost-effective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band power amplifier (PA), the position of the inverse system is exchanged during the identification procedure to avoid the necessity of a PA model within a cumbersome closed-loop process. However, in a practical environment where only an approximation to the inverse is achieved, the linearization capability is affected by shifting the post-inverse placed after the PA to a pre-inverse located before the PA. In DPD intended for concurrent dual-band PAs, an additional advantage of such approach is that the post-inverse identifications for each band are completely independent of each other. This work performs a comparative analysis between two learning architectures applied to the linearization of two concurrent dual-band PAs stimulated by 2.4 GHz Wi-Fi and 3.5 GHz LTE signals. For the first PA, an exact PA model is known and the replacement of a post-inverse to a pre-inverse produces only negligible degradation in linearity. For the second PA, only an approximate PA model is available and the accuracy of such PA model produces a major impact on the linearization capability than the shifting of the inverse.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129717590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA hardware linear regression implementation using fixed-point arithmetic 用FPGA实现硬件线性回归的定点算法

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339853

W. D. A. P. Ferreira, I. Grout, A. M. Silva

引用次数: 6

New Insight for next Generation SRAM: Tunnel FET versus FinFET for Different Topologies 新一代SRAM:隧道场效应管与不同拓扑结构的FinFET

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339871

Adriana Arevalo, Romain Liautard, Daniel Romero, L. Trojman, L. Prócel

引用次数: 4

Behavioral Modeling of a Control Module for an Energy-investing Piezoelectric Harvester 能量投资型压电采集器控制模块的行为建模

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339855

Tales Luiz Bortolin, A. Aita, J. B. Martins

引用次数: 2

Exploring Tabu Search Based Algorithms for Mapping and Placement in NoC-based Reconfigurable Systems 探索基于禁忌搜索的可重构系统中映射和放置算法

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339843

Guilherme Apolinario Silva Novaes, L. C. Moreira, W. Chau

引用次数: 4

Lightweight Security Mechanisms for MPSoCs mpsoc的轻量级安全机制

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339876

A. Sant'Ana, Henrique Martins Medina, Kevin Boucinha Fiorentin, F. Moraes

{"title":"Lightweight Security Mechanisms for MPSoCs","authors":"A. Sant'Ana, Henrique Martins Medina, Kevin Boucinha Fiorentin, F. Moraes","doi":"10.1145/3338852.3339876","DOIUrl":"https://doi.org/10.1145/3338852.3339876","url":null,"abstract":"Computational systems tend to adopt parallel architectures, by using multiprocessor systems-on-chip (MPSoCs). MPSoCs are vulnerable to software and hardware attacks, as infected applications and Hardware Trojans respectively. These attacks may have the purpose to gain access to sensitive data, interrupt a given application or even damage the system physically. The literature presents countermeasures using dedicated routing algorithms, cryptography, firewalls and secure zones. These approaches present a significant hardware cost (firewalls, cryptography) or are too restrictive regarding the use of MPSoC resources (secure zones). The goal of this paper is to present lightweight security mechanisms for MPSoCs, using four techniques: spatial isolation of applications; dedicated network to send sensitive data; traffic blocking filter; lightweight cryptography. These mechanisms protect the MPSoC against the most common software attacks, as Denial of Service (DoS) and spoofing (man-in-the-middle), and ensures confidentiality and integrity to applications. Results present low area and latency overhead, as well as the effectiveness of using the mechanisms to block malicious traffic.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"13 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131754785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Energy efficient fJ/spike LTS e-Neuron using 55-nm node 采用55-nm节点的高效fJ/spike LTS e-Neuron

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339852

Pietro M. Ferreira, Nathan De Carvalho, G. Klisnick, Aziz Benlarbi-Delaï

{"title":"Energy efficient fJ/spike LTS e-Neuron using 55-nm node","authors":"Pietro M. Ferreira, Nathan De Carvalho, G. Klisnick, Aziz Benlarbi-Delaï","doi":"10.1145/3338852.3339852","DOIUrl":"https://doi.org/10.1145/3338852.3339852","url":null,"abstract":"While CMOS technology is currently reaching its limits in power consumption and circuit density, a challenger is emerging from the analogy between biology and silicon. Hardware-based neural networks may drive a new generation of bio-inspired computers by the urge of a hardware solution for real-time applications. This paper redesigns a previous proposed electronic neuron (e-Neuron) in a higher firing rate to reduce the silicon area and highlight a better energy efficiency trade-off. Besides, an innovative schematic is proposed to state an e-Neuron library based on Izhikevichs model of neural firing patterns. Both e-Neuron circuits are designed using 55 nm technology node. Physical design of transistors in weak inversion are discussed to a minimal leakage. Neural firing pattern behaviors are validated by post-layout simulations, demonstrating the spike frequency adaptation and the rebound spikes due to post-inhibitory effect in LTS e-Neuron. Presented results suggest that the time to rebound spikes is dependent of the excitation current amplitude. Both e-Neurons have presented a fF/spike energy efficiency and a smaller silicon area in comparison to Izhikevichs library propositions in the literature.","PeriodicalId":184401,"journal":{"name":"2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"32 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Hardware Design of DC/CFL Intra-Prediction Decoder for the AV1 Codec AV1编解码器DC/CFL内预测解码器硬件设计

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339873

J. Goebel, B. Zatt, L. Agostini, M. Porto

引用次数: 6

A new algorithm for an incremental sigma-delta converter reconstruction filter 增量式σ - δ变换器重构滤波器的新算法

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI) Pub Date : 2019-08-26 DOI: 10.1145/3338852.3339839

Li Huang, C. Lelandais-Perrault, A. Kolar, P. Bénabès

引用次数: 3