Hardware Design of DC/CFL Intra-Prediction Decoder for the AV1 Codec

J. Goebel, B. Zatt, L. Agostini, M. Porto
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引用次数: 6

Abstract

This paper presents a dedicated hardware design for the DC and Chroma from Luma (CFL) intra-prediction modes of AV1 decoder. The hardware was designed to reach real-time when processing UHD 4K videos. The AV1 codec is an open-source and royalties-free video coding, which was developed by the AOMedia group, this group is composed of multiple companies like Google, Netflix, AMD, ARM, Intel, Nvidia, Microsoft, Mozilla and others. The proposed solution can support all 19 block sizes allowed in AV1 encoder, being able to process UHD 4K videos at 60 frames per second. The DC/CFL modules were synthesized to the TSMC 40 nm cells library targeting the frequency of 132.1 MHz. Synthesis results show the proposed hardware used 89.39 Kgates and a power dissipation of 7.96mW.
AV1编解码器DC/CFL内预测解码器硬件设计
本文介绍了AV1解码器的DC和CFL内预测模式的专用硬件设计。硬件设计是为了在处理超高清4K视频时达到实时。AV1编解码器是一种开源且免版税的视频编码,由AOMedia集团开发,该集团由多家公司组成,如Google, Netflix, AMD, ARM, Intel, Nvidia, Microsoft, Mozilla等。提出的解决方案可以支持AV1编码器允许的所有19个块大小,能够以每秒60帧的速度处理UHD 4K视频。DC/CFL模块合成到TSMC 40 nm单元库中,目标频率为132.1 MHz。综合结果表明,该硬件使用89.39 Kgates,功耗为7.96mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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