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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)最新文献

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Nonlinear Equivalent Circuit Model Base on BPNN for GaN HEMTs 基于bp神经网络的GaN hemt非线性等效电路模型
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754355
Manli Xue, Lu Sun, Shuo Wang, Peipei Liang, Xiaolong Chen, F. Nian
{"title":"Nonlinear Equivalent Circuit Model Base on BPNN for GaN HEMTs","authors":"Manli Xue, Lu Sun, Shuo Wang, Peipei Liang, Xiaolong Chen, F. Nian","doi":"10.1109/EDSSC.2019.8754355","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754355","url":null,"abstract":"A Back-Propagation Neural Network (BPNN) nonlinear model of $GaN$ HEMT is proposed, which can adaptively fit the nonlinear parameter relationship, and reduce computation. The network weights are obtained automatically, and then the nonlinear mapping relation is determined. The comparison between BPNN model and test data proves the good consistency.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121609159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An expression for oscillation amplitude of NMOS/PMOS complementary cross-coupled LC-tank oscillator NMOS/PMOS互补交叉耦合LC-tank振荡器振荡幅值表达式
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754367
Feng Zhang, Chunyu Ma, Ting Zhao
{"title":"An expression for oscillation amplitude of NMOS/PMOS complementary cross-coupled LC-tank oscillator","authors":"Feng Zhang, Chunyu Ma, Ting Zhao","doi":"10.1109/EDSSC.2019.8754367","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754367","url":null,"abstract":"Oscillation amplitude is a key factor for NMOS/PMOS complementary cross-coupled LC-tank oscillator, and its proper estimation is beneficial to design oscillator and select process. An ordinary expression for oscillation amplitude of NMOS/PMOS complementary cross-coupled LC-tank oscillator is derived by solving Shichman-Hodge equation using Fourier Transform. It mainly depends on power supply voltage and threshold voltage. The effects of power supply voltages, transistor’s sizes and inductor values are discussed. The calculation and Cadence simulation of oscillation amplitude show excellent agreement with error less than 5%.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114210977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Snapback Suppressed Base Resistance Controlled Thyristor with Double N-type Buried Layer 双n型埋层回跳抑制基极电阻控制晶闸管
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753932
Fei Hu, Limei Song, Zhengsheng Han, Huan Du, Jiajun Luo
{"title":"A Snapback Suppressed Base Resistance Controlled Thyristor with Double N-type Buried Layer","authors":"Fei Hu, Limei Song, Zhengsheng Han, Huan Du, Jiajun Luo","doi":"10.1109/EDSSC.2019.8753932","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753932","url":null,"abstract":"A new base resistance controlled thyristor with double N-type buried layer (DNBL-BRT) is proposed in this paper. In the new structure, the left N-buried layer introduces an electron potential trap to extract electron current into thyristor, then effective thyristor trigger current is enhanced. Meanwhile, the right N-buried layer acts as a hole potential barrier to push hole current into P-base region, then parasitic PNP is suppressed and hole current density in P-base region is improved. Snapback phenomenon is significantly suppressed. Numerical simulation results show that, snapback-free can be realized when the doping level of N-buried layers is $1.0 times 10^{15}$ $mathrm{c m}^{-3}$and the distance between the two N-buried layers is 1.5 $mu$m, meanwhile high blocking capability is maintained.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121230217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Design and Analysis of Dual-mode Antenna Reflector 双模天线反射器的设计与分析
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753968
Lu Dong, Zelun Zhou, Yong Huang, Xi Chen, Kai Yang, Xi Li
{"title":"The Design and Analysis of Dual-mode Antenna Reflector","authors":"Lu Dong, Zelun Zhou, Yong Huang, Xi Chen, Kai Yang, Xi Li","doi":"10.1109/EDSSC.2019.8753968","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753968","url":null,"abstract":"Firstly, several common-aperture schemes of millimeter-wave/infrared (MMW/IR) dual-mode antenna systems are introduced. The key of these dual-mode antenna systems is the design of antenna reflector with the function of millimeter wave transmission and infrared reflection. Then, cross-ring gap frequency selective surface (FSS) is proposed to achieve this function, and the feasibility of designed structure is proved by HFSS simulation.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Methodology of Building Power System on Chip 一种构建片上电力系统的有效方法
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754058
Zixuan Zhao, Xuan Luo, Jia Wang, Xiaomin Wei, R. Zheng, Yann Hu
{"title":"An Efficient Methodology of Building Power System on Chip","authors":"Zixuan Zhao, Xuan Luo, Jia Wang, Xiaomin Wei, R. Zheng, Yann Hu","doi":"10.1109/EDSSC.2019.8754058","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754058","url":null,"abstract":"The regulator number and location are critical issues in the design of power system on chip. In order to achieve optimized number and location of the regulators, an efficient methodology of building power system on chip is proposed. All loads are firstly divided into their own voltage domain, where only one regulator supplies power. The voltage domain is built and continues developing, till the sum of the load current exceeds the maximum output current of regulator. The optimized location of regulator is calculated by the particle swarm optimization (PSO). The time and memory required are reduced. The proposed algorithm has been realized by MATLAB. The results were verified by IBM power grid analysis benchmarks. Compared with the IBM benchmarks’ own power distribution, voltage drop is decreased by the proposed algorithm.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132663170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Multi-Channel Synchronous Sampling Circuit Based on Ultra-Wideband 基于超宽带的多通道同步采样电路设计
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754033
Xu Rui-rong, Liang Chun-lai, Huang Jin-xian, Li Ren-gang, Song Shi-qian, Wang Ning
{"title":"Design of Multi-Channel Synchronous Sampling Circuit Based on Ultra-Wideband","authors":"Xu Rui-rong, Liang Chun-lai, Huang Jin-xian, Li Ren-gang, Song Shi-qian, Wang Ning","doi":"10.1109/EDSSC.2019.8754033","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754033","url":null,"abstract":"The performance of sampling chip is critical to the performance of the digital receiving system. The paper proposes an implementation solution of high-performance multi-channel synchronous sampling circuit with $4GHz$ instantaneous bandwidth and 10.24Gsps sampling rate which is based on the domestic high-speed ADC chip. The paper mainly describes the design of high-speed ADC chip, which includes register control, power supply design, clock design, and interface design. Lastly, the design and debugging of software and hardware are carried out as per the functional requirements of the boards. According to the result of experimental test, the FPGA is able to receive the multi-channel ultra-wideband high-frequency signal generated by the signal generator perfectly, which means that the synchronous sampling design based on high-speed ADC chip is able to satisfy the design requirements and accomplishes the purpose of 10.24Gsps sampling and $4GHz$ bandwidth synchronous signal reception.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133245049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Read-Decoupled Radiation Hardened RD-DICE SRAM Cell for Low-Power Space Applications 用于低功耗空间应用的读去耦辐射硬化RD-DICE SRAM单元
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753939
Mili Lavania, Neelam Surana, Ishant Anand, Joycee Mekie
{"title":"Read-Decoupled Radiation Hardened RD-DICE SRAM Cell for Low-Power Space Applications","authors":"Mili Lavania, Neelam Surana, Ishant Anand, Joycee Mekie","doi":"10.1109/EDSSC.2019.8753939","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753939","url":null,"abstract":"Conventional 6T Static Random Access Memory(SRAM) cell suffers from data flip (Single event upset) due to continuous bombardment of radiation particles in the space environment. To mitigate single-event upset (SEU) which arises due to radiation, radiation-hardened SRAM cell such as dual interlocked storage cell (DICE) is proposed in the literature. However, DICE SRAM uses 4 bit-lines for the read and write operations, and which consume significantly high power when compared with the conventional 6T SRAM cell with 2 bit-lines. To resolve this issue, we propose a read-decoupled DICE SRAM cell, which uses only single bit-line for a read operation. Simulations results obtained from Spice for 1 KB SRAM array implemented in UMC 65nm and SCL 180nm technology node show that by simply decoupling read and write operation in DICE SRAM, read energy(write energy) and read delay(write delay) reduce by at least 72 %(17%) and 67%(37%) respectively. SEU results obtained from Cogenda tool show that the read-decoupled DICE is immune to radiations as is DICE.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Effect of Encapsulation on the Resistive Switching Characteristics of Gama-minopropyltriethoxysilane Layer 封装对γ -米丙基三乙氧基硅烷层电阻开关特性的影响
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8753920
You-Lin Wu, Jing-Jenn Lin, Sung-Lin Tsai
{"title":"Effect of Encapsulation on the Resistive Switching Characteristics of Gama-minopropyltriethoxysilane Layer","authors":"You-Lin Wu, Jing-Jenn Lin, Sung-Lin Tsai","doi":"10.1109/EDSSC.2019.8753920","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8753920","url":null,"abstract":"Passivation or encapsulation is generally required for organic layers because they are easily attacked by ambient oxygen or water vapor, causing property deterioration. It has been reported that gammaaminopropyltriethoxysilane ($gamma$-APTES), an amino-functional organosilane material, can exhibit resistive switching behavior. In this work, we investigated the effect of encapsulation on the resistive switching characteristics of the $gamma$-APTES layer. We found that the switching voltages as well as the resistances of high-resistance state (RHRS) and resistance of low-resistances state (RLRS) of encapsulated $gamma$-APTES layers were different from those of non-encapsulated ones. The causes for these differences in the resistive switching characteristics between the encapsulated and non-encapsulated $gamma$-APTES layer are discussed.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133592449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal design of power GaN HEMT field plate structure 功率GaN HEMT场极板结构优化设计
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754401
D. Shuai, G. Weiling, Lei Liang, Lin Tianyu
{"title":"Optimal design of power GaN HEMT field plate structure","authors":"D. Shuai, G. Weiling, Lei Liang, Lin Tianyu","doi":"10.1109/EDSSC.2019.8754401","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754401","url":null,"abstract":"GaN as the third generation semiconductor material has good prospects for development. The wide bandgap of GaN enables it to work at high temperature, and has higher breakdown voltage and better breakdown characteristics. The structure of AlGaN/GaN based high electron mobility transistor (AlGaN/GaN HEMT) is simulated and analyzed by using simulation software Silvaco ATLAS. Firstly, the effect of field plate structure on breakdown voltage is introduced, and then the effect of field plate length on breakdown voltage of devices is analyzed. The results show that the change of field plate length has great influence on breakdown voltage, and the optimal value is determined by testing, which has practical guiding significance for the actual device fabrication.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132284280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Effective Method of Reducing TSV Thermal Stress by STI STI降低TSV热应力的有效方法
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI: 10.1109/EDSSC.2019.8754330
F. Wang, Xiaoqing Qu, N. Yu
{"title":"An Effective Method of Reducing TSV Thermal Stress by STI","authors":"F. Wang, Xiaoqing Qu, N. Yu","doi":"10.1109/EDSSC.2019.8754330","DOIUrl":"https://doi.org/10.1109/EDSSC.2019.8754330","url":null,"abstract":"Because of the increasing integration of the chip, three-dimensional integrated circuit (3-D IC) has emerged to resolve the problem, but 3-D integration is also facing more serious challenges, such as thermal stress. The thermal stress of through-silicon via (TSV) structure affects device performance and causes severe reliability problems by reducing carrier mobility. In this paper, we propose an effective method to reduce the thermal stress of TSV by means of shallow trench isolation (STI). We use Cu and silicon dioxide as materials, evaluating the thermal stresses with finite element analysis (FEA) and comparing the stresses in different situations. Finally we derive the stress data and calculate the keep-out zone (KOZ) of the different structures and find that STI can reduce the TSV thermal stress by 10.3~25.S%.","PeriodicalId":183887,"journal":{"name":"2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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