Design of Multi-Channel Synchronous Sampling Circuit Based on Ultra-Wideband

Abstract

The performance of sampling chip is critical to the performance of the digital receiving system. The paper proposes an implementation solution of high-performance multi-channel synchronous sampling circuit with $4GHz$ instantaneous bandwidth and 10.24Gsps sampling rate which is based on the domestic high-speed ADC chip. The paper mainly describes the design of high-speed ADC chip, which includes register control, power supply design, clock design, and interface design. Lastly, the design and debugging of software and hardware are carried out as per the functional requirements of the boards. According to the result of experimental test, the FPGA is able to receive the multi-channel ultra-wideband high-frequency signal generated by the signal generator perfectly, which means that the synchronous sampling design based on high-speed ADC chip is able to satisfy the design requirements and accomplishes the purpose of 10.24Gsps sampling and $4GHz$ bandwidth synchronous signal reception.