{"title":"Reconfigurable fault tolerant binary tree-implementation in two-dimensional arrays and reliability analysis","authors":"I. Takanami, K. Inoue, T. Watanabe","doi":"10.1109/ICWSI.1994.291258","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291258","url":null,"abstract":"We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array In which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L/sub 0/ into a rectangular array, which is called a root module. For levels L(>L/sub 0/), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124605843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal chip sizing for hybrid-WSI","authors":"P. Singh, D. Landis","doi":"10.1109/ICWSI.1994.291231","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291231","url":null,"abstract":"The inter-chip delay penalty for hybrid-WSI and MCM designs is much lower than that for printed wiring boards. Consequently, the system partitioning and die size optimization problems must be attacked using a different set of parameters. This paper develops a new figure of merit for optimal HWSI/MCM chip sizing based upon system quality level, cost, and silicon efficiency. The figure of merit is then applied to a 500k gate MCM case study.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125312717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Quasi-analytical analysis of the broadband properties of multiconductor transmission lines on semiconducting substrates","authors":"E. Groteluschen, L. S. Dutta, S. Zaage","doi":"10.1109/ICWSI.1994.291230","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291230","url":null,"abstract":"The electrical properties of single and coupled transmission lines on semiconductor substrates are investigated. The analysis is based on analytical formulas for the frequency-dependent distributed line impedances and admittances. Using these formulas it is possible to characterize the broadband properties of transmission line systems with a minimal amount of computational effort. The validity of the calculated results is proved by comparison with full-wave analyses and experimental data gained from on-chip measurements. A discussion of the calculated line parameters as functions of frequency and substrate conductivity is given. Finally, the influence of the semiconducting substrate on the signal propagation in the time domain is demonstrated by two examples.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125904968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WSI evolution: increasing cell size to generalize designs","authors":"S. Millman","doi":"10.1109/ICWSI.1994.291255","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291255","url":null,"abstract":"The current state of the art of wafer-scale integration is explored in this paper. Problems which must be solved to generalize the applicability of products using wafer-scale integration are also discussed. The goal of this paper is to provide a framework for discussion on the future of wafer-scale integration, as well as to provide topics for future research.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127877756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"What designers of wafer scale systems should know about local sparing","authors":"L. LaForge","doi":"10.1109/ICWSI.1994.291259","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291259","url":null,"abstract":"Local sparing is a simple way to organize the redundancy of a fault tolerant system. Any system can be locally spared. Furthermore, local sparing preserves both regularity and planarity. In spite of this, the potential usefulness of local sparing appears to have been overlooked. Suppose that the designer wishes to assure, with high probability, a fault-free copy of the n-element system desired. If local sparing is used then, as proved, i) the resulting area is /spl Theta/(log n) times the area of the system desired; ii) the wire length is /spl Oscr/(/spl radic/(log n)) times the maximum wirelength in the desired system; iii) an optimal diagnosis algorithm identifies the faulty elements in /spl Theta/(n log/sup 2/ n) time; iv) in optimal time /spl Theta/(n log n+number of wires in the desired system), a simple configuration algorithm achieves a fault-free copy of the desired system if and only if a fault-free copy exists. The authors illustrate these results for arrays, binary trees, and hypercubes. In addition, v) if Y denotes the probability of achieving a fault-free copy of the system desired then, using h-fold redundancy, the maximum rate at which elements can fail is ((/spl minus/ln Y)/n)/sup 1/h/. Local sparing is simple, widely-applicable, and low-cost. A disadvantage is that, depending on the system desired, the cost may not be optimal. However, there is strong reason to prefer local sparing over global sparing, and in some cases local sparing is better than more popular approaches to configuration.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Progress and status of the WASP3 WSI massively parallel processor","authors":"I. Jalowiecki","doi":"10.1109/ICWSI.1994.291236","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291236","url":null,"abstract":"The ASP (Associative String Processor) is a massively parallel fault tolerant associative processor designed for the implementation of extensible parallel processing systems. This paper describes the latest status on the WASP3 processor, which is an implementation of an ASP processor array, comprising a large monolithic device (5.5 cm/spl times/5.5 cm) laminated with an MCM-D High Density Interconnect (HDI) substrate to provide signal and power connectivity.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124127543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of laser link crossbar and Omega network switching for wafer-scale integration defect avoidance","authors":"G. H. Chapman, K. Fang","doi":"10.1109/ICWSI.1994.291238","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291238","url":null,"abstract":"A study is presented of the design tradeoffs between two wafer scale defect avoidance methods: laser linking and active switches. Laser linking methods use laser processing to make signal line connections and cuts. Alternately active transistor switching elements, like the Omega network, can circumvent defects. WSI systems would benefit from a combination of both methods. The requirements of both for silicon area, signal delay, power consumption, probable switch yield and defect avoidance flexibility are considered. As an experimental vehicle an 8/spl times/8 Omega network and laser link crossbar switch was fabricated and tested.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124457085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}