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Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)最新文献

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Optimizing reliability in a two-level distributed architecture for wafer scale integration 面向晶圆规模集成的两级分布式架构可靠性优化
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291243
J. Samson
{"title":"Optimizing reliability in a two-level distributed architecture for wafer scale integration","authors":"J. Samson","doi":"10.1109/ICWSI.1994.291243","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291243","url":null,"abstract":"Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. The Reliability-Hardware Quotient (RHQ) is an example of a fundamental composite metric which is useful for identifying the optimal design point in a VSLI or wafer scale system. In this paper, the RHQ metric is applied to the problem of optimizing a two-level distributed (parallel) processing architecture. In particular, a graphical optimization technique using the 3D and contour plot features of Mathematica is introduced which characterizes the trade space and identifies the optimum design point. The constraints of wafer scale technology can be superimposed upon the optimal solution space either to identify the limits of a given wafer scale implementation or to show what level of wafer scale technology is needed to achieve the optimum design.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117147803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integration scale increase of processor-arrays by using hierarchical redundancy 利用分层冗余提高处理器阵列集成规模
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291241
N. Tsuda
{"title":"Integration scale increase of processor-arrays by using hierarchical redundancy","authors":"N. Tsuda","doi":"10.1109/ICWSI.1994.291241","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291241","url":null,"abstract":"This paper specifies the relationships between WSI array structures and the maximum WSI integration scales possible when using hierarchical k-out-of-n redundancy configurations having expanded hierarchical levels. An estimate using five kinds of one-dimensional/two-dimensional array-connection models indicates that four-level redundancy configurations can increase the maximum possible integration scales 4 to 64 times over that achieved by single-level configurations according to the complexity of the array-connections. This feature is based on the distribution of defect-tolerance load into the hierarchical structures enhanced by expanding the hierarchical levels.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116365740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimal reconfiguration of WSI multipipeline arrays WSI多管道阵列的优化重构
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291257
J. Salinas, C. Feng, J. Wall, F. Lombardi
{"title":"Optimal reconfiguration of WSI multipipeline arrays","authors":"J. Salinas, C. Feng, J. Wall, F. Lombardi","doi":"10.1109/ICWSI.1994.291257","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291257","url":null,"abstract":"This paper presents a new algorithm for reconfiguring WSI multipipeline arrays in the presence of faults in links, processing elements (PE's) and switching elements (SE's). Using a fault model in which a PE and link can be either fault free or faulty and a SE is modeled by relating its switching capabilities to its status and the status of the connecting links, it is proved that an algorithm which maximizes the number of reconfigured pipelines (optimality) is possible in an execution complexity lower than a previous algorithm based on a maximum flow approach. The proposed approach is based on a greedy algorithm with an execution complexity of O(n/spl times/m), where n is the number of stages (or columns) of the array and m is the number of PE's in a stage.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"51 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116532271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems 一种在单片- wsi系统中提高时钟频率和通信速度的体系结构方法
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291248
D. Audet, Y. Savaria, N. Arel
{"title":"An architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems","authors":"D. Audet, Y. Savaria, N. Arel","doi":"10.1109/ICWSI.1994.291248","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291248","url":null,"abstract":"Based on special pipelining techniques, a new methodology for increasing the clock frequency and communication speed in monolithic-WSI systems is proposed. Spice simulations show that the clock frequency on wafer scale systems implemented using a 1.2 micron CMOS technology can be operated well above 140 MHz, which is approximatively five times the maximum frequency of current systems. It is also shown that pipelining principles can be applied to communication links. That particular strategy allows to speedup communication transfers on 5 cm interconnection wires, such as those running across a wafer, by a factor between two and ten, as compared to the case in which no pipelining is used.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132319109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Integrated diagnosis and reconfiguration process for defect tolerant WSI processor arrays 容错WSI处理器阵列的集成诊断与重构过程
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291233
Kuochen Wang, Jenn-Wei Lin
{"title":"Integrated diagnosis and reconfiguration process for defect tolerant WSI processor arrays","authors":"Kuochen Wang, Jenn-Wei Lin","doi":"10.1109/ICWSI.1994.291233","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291233","url":null,"abstract":"This paper presents a new technique for constructing a fault-free subarray from a defective WSI (wafer scale integration) processor array based on an integrated diagnosis and reconfiguration (IDAR) method. In a traditional yield enhancement approach, it diagnoses all units first and then the status (faulty or fault-free) of all units are passed to the reconfiguration algorithm for a possible reconfiguration solution. The basis of the IDAR method is that reconfiguration can be performed under partial diagnosis information. Systematic analysis has been used to formulate the IDAR process and to estimate the minimal size of a target array at which we need to diagnose all units. We also compare the yield enhancement cost of our approach with that of other strategies.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126163614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Image processing using a universal nonlinear cell 图像处理采用通用非线性单元
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291234
V. Jain, L. Lin
{"title":"Image processing using a universal nonlinear cell","authors":"V. Jain, L. Lin","doi":"10.1109/ICWSI.1994.291234","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291234","url":null,"abstract":"Silicon implementation of many image processing algorithms has been hindered in the past due to their complexity and computational volume. This paper discusses two such algorithms, namely the 'Detection of line segments via Hough transform' and 'Backprojection in CT image reconstruction'. To gain a significant speed advantage, we present a multi-function cell for performing one of four nonlinear operations: (1) square-root, (2) reciprocal, (3) sine/cosine, and (4) arctangent/spl minus/all realized in a single chip, available on a selectable basis, and outputting a new result every two clock cycles. The design and test results of a 24 bit and a 16 bit four-function \"two cycle\" VLSI chip, both fabricated in 2.0 micron CMOS technology, are described. Also discussed is a new \"one-cycle\" architecture, which can potentially double the throughput of the chip. Using this nonlinear cell an application level Hough transform module is developed. The Hough module can deliver parameters of the line in the image plane every clock cycle.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129021079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
WSI design of a radix 2 butterfly using macrocell pools 基于宏细胞池的基数2蝴蝶的WSI设计
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291239
T. K. Callaway, E. Swartzlander
{"title":"WSI design of a radix 2 butterfly using macrocell pools","authors":"T. K. Callaway, E. Swartzlander","doi":"10.1109/ICWSI.1994.291239","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291239","url":null,"abstract":"The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. At the circuit level, the strategy used is macrocell pooled redundancy. There are two basic types of macrocell pooled redundancy: 1 from N, and M from N. These two strategies are applied to the design of a radix 2 butterfly circuit for an FFT processor, and the effects of the choice of pooling strategy upon the yield are shown.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An effective framework for fault-tolerant VLSI/WSI arrays based on hybrid redundancy approach 基于混合冗余方法的VLSI/WSI阵列容错有效框架
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291256
Yung-Yuan Chen, Yung-Shiuan Shyu, Ching-Hwa Cheng
{"title":"An effective framework for fault-tolerant VLSI/WSI arrays based on hybrid redundancy approach","authors":"Yung-Yuan Chen, Yung-Shiuan Shyu, Ching-Hwa Cheng","doi":"10.1109/ICWSI.1994.291256","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291256","url":null,"abstract":"Proposes a formal hybrid redundancy approach based on the concepts as follows: block partitioning, local reconfiguration and spare sharing, and spare borrowing from upper, lower, and right corresponding blocks. This systematic approach combined the concepts indicated and allows reconfiguration schemes of varying complexity and performance to develop. Two reconfiguration algorithms within such a framework are presented. The authors then develop the switching interconnection networks to support the reconfiguration algorithms proposed. The Markov model combined with the combinatorial model is used to analyze the system yield, and then the Monte Carlo simulation is conducted to justify the theoretical analysis. Finally, they perform the comparisons among the algorithms proposed with other representative algorithms to validate the schemes. The significance of this research is to propose a new framework which can be used to derive a suitable and effective redundancy scheme for a specific application and requirements.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115667930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Wafer-scale integration as a technology choice for high speed ATM switching systems 晶圆级集成作为高速ATM交换系统的技术选择
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291244
N. Mirfakhraei
{"title":"Wafer-scale integration as a technology choice for high speed ATM switching systems","authors":"N. Mirfakhraei","doi":"10.1109/ICWSI.1994.291244","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291244","url":null,"abstract":"This paper presents a new architecture of multigigabit ATM switching system using wafer-scale integration (WSI). Clearly, the crucial delay constraints in a switching network using discrete VLSI components fall within the off-chip interconnections. We propose the use of WSI to facilitate higher speed operation. WSI allows us to consider new design alternatives that would not be practical in a system using discrete components. In the architecture presented in this paper, identical units called self-driven crosspoints will make up the entire ATM switching fabric in a wafer-scale system.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122931275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A single-chip digital signal processing system 一种单片机数字信号处理系统
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291232
J. E. Brewer, L. G. Miller, I. H. Gilbert, J. F. Melia, D. Garde
{"title":"A single-chip digital signal processing system","authors":"J. E. Brewer, L. G. Miller, I. H. Gilbert, J. F. Melia, D. Garde","doi":"10.1109/ICWSI.1994.291232","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291232","url":null,"abstract":"A single-chip 26 million transistor digital processing subsystem is in the final stages of development. This general purpose device can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arrays. This 120 MFLOPS peak 1.75 watt chip, with 512 k-bytes of on-chip SRAM and sophisticated communications capabilities, requires no glue chips to form processors arrays. This paper describes the physical and functional features of the integrated circuit, and outlines its application potential.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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