Optimizing reliability in a two-level distributed architecture for wafer scale integration

J. Samson
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引用次数: 1

Abstract

Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. The Reliability-Hardware Quotient (RHQ) is an example of a fundamental composite metric which is useful for identifying the optimal design point in a VSLI or wafer scale system. In this paper, the RHQ metric is applied to the problem of optimizing a two-level distributed (parallel) processing architecture. In particular, a graphical optimization technique using the 3D and contour plot features of Mathematica is introduced which characterizes the trade space and identifies the optimum design point. The constraints of wafer scale technology can be superimposed upon the optimal solution space either to identify the limits of a given wafer scale implementation or to show what level of wafer scale technology is needed to achieve the optimum design.<>
面向晶圆规模集成的两级分布式架构可靠性优化
在许多系统应用中,支持任务寿命可靠性的容错是一个关键考虑因素。自晶圆级技术出现以来,缺陷容限冗余,即良率提高和晶圆级可靠性提高已成为标准做法。可靠性-硬件商(RHQ)是一个基本的复合度量的例子,它有助于在VSLI或晶圆规模系统中确定最佳设计点。本文将RHQ指标应用于两级分布式(并行)处理体系结构的优化问题。特别介绍了利用Mathematica软件的三维和等高线绘图特性的图形化优化技术,该技术可以表征贸易空间并确定最佳设计点。晶圆规模技术的约束可以叠加在最优解决方案空间上,以确定给定晶圆规模实施的限制,或显示需要何种水平的晶圆规模技术来实现最佳设计。
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