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Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)最新文献

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Silicon wafer-area network: intelligent communications fabric for parallel computing 硅片区域网络:用于并行计算的智能通信结构
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291237
I.V. Petrova, M.T. Uppuluri, S. Tewksbury, L. Hornak
{"title":"Silicon wafer-area network: intelligent communications fabric for parallel computing","authors":"I.V. Petrova, M.T. Uppuluri, S. Tewksbury, L. Hornak","doi":"10.1109/ICWSI.1994.291237","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291237","url":null,"abstract":"The SWAN (silicon wafer-area network) project described explores the application of the high speed and high density of interconnections in WSI and MCM technologies to new communications schemes for general purpose, parallel arrays of computing nodes. The SWAN architecture seeks to provide on-demand, point-to-point communications through dynamically allocated routes for fine-grained communications.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116382464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a large area magnetic field sensor array 大面积磁场传感器阵列的设计
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291245
Y. Audet, G. Chapman
{"title":"Design of a large area magnetic field sensor array","authors":"Y. Audet, G. Chapman","doi":"10.1109/ICWSI.1994.291245","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291245","url":null,"abstract":"The circuit design of a Large Area Magnetic Field Sensor Array (LAMFSA) using CMOS 3 /spl mu/m process is described. This prototype is developed mainly for application in magnetic field mapping and tactile array sensors. In order to enable the production of such a device, redundancy schemes are implemented and a laser interconnection post fabrication technique is used. The basic sensing cell consists of a double drain/double source MOS magnetic field sensor (MAGFET). The design architecture is strongly influenced by the sensor function and the defect avoidance criteria. Aided by SPICE, test and reconfiguration issues involved in the post fabrication processing are described.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121493127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cycles analysis for testability of WSI sequential architectures WSI顺序体系结构可测试性的周期分析
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291252
M. Bombana, G. Buonanno, P. Cavalloro, Fabrizio Ferrandi, D. Sciuto, G. Zaza
{"title":"Cycles analysis for testability of WSI sequential architectures","authors":"M. Bombana, G. Buonanno, P. Cavalloro, Fabrizio Ferrandi, D. Sciuto, G. Zaza","doi":"10.1109/ICWSI.1994.291252","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291252","url":null,"abstract":"Testability analysis can he performed through classification of all possible simple interconnection topologies, definition of testability conditions on the functions performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feed-forward architectures are studied. Application of such approach to irregular architectures with cycles (signal feedbacks) is presented in this paper.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design for diagnosability and diagnostic strategies of WSI array architectures WSI阵列架构的可诊断性和诊断策略设计
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291251
Kuochen Wang, W. Tseng
{"title":"Design for diagnosability and diagnostic strategies of WSI array architectures","authors":"Kuochen Wang, W. Tseng","doi":"10.1109/ICWSI.1994.291251","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291251","url":null,"abstract":"An efficient fault diagnosis method for defect-tolerant reconfigurable WSI array architectures is proposed. We use a systolic array as an example array architecture. The basic idea is to utilize the vertical scan paths and horizontal scan paths to partition a two-dimensional systolic array under test into disjoint blocks, and each block can then be tested concurrently, thus the testing time is reduced significantly. A modification version of the reconfigurable array called a full serial scan (FSS) array is also proposed to reduce the hardware overhead of the original design. The significance of our approach is providing an efficient two-dimensional reconfigurable systolic array which is easily diagnosable and the yield enhancement of the array is demonstrated. Furthermore, the design approach can be easily extended to other parallel architectures.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122597142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reducing cost and ensuring on-time delivery of hybrid-WSI massively parallel computing modules 降低混合- wsi大规模并行计算模块的成本并保证准时交付
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291250
C. Habiger, R. Lea
{"title":"Reducing cost and ensuring on-time delivery of hybrid-WSI massively parallel computing modules","authors":"C. Habiger, R. Lea","doi":"10.1109/ICWSI.1994.291250","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291250","url":null,"abstract":"Hybrid-WSI technologies offer an attractive implementation route for Massively Parallel Computing (MPC) Modules. However, cost and, especially, delivery problems, still associated with these technologies make MPC manufacturers wary. Uncertainties are mainly caused by limited individual die yields, and loss of good die during the mounting and bonding processes. Although significant research effort is aimed at supplying \"known-good-die\" and die yields can be expected to improve in the near future, these are likely to be superseded by increased levels of integration. This paper demonstrates how redundancy and reconfiguration can offer a solution to the problem and ensure on-time delivery while reducing the production cost of hybrid-WSI MPC modules significantly.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123462601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Clock synchronization for WSI systems WSI系统的时钟同步
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291249
S. Embabi, D. Brueske
{"title":"Clock synchronization for WSI systems","authors":"S. Embabi, D. Brueske","doi":"10.1109/ICWSI.1994.291249","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291249","url":null,"abstract":"This paper presents a clock synchronisation method which can be used to reduce the clock skew time in WSI systems. A feedback technique is used to offset the clock skewing due to process mismatches and environmental variations. Experiments and simulations indicate that the skew time can be reduced to within a few tens of picoseconds. The stability analysis shows that the system is stable under certain conditions which can be easily satisfied.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124195489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault tolerant multicube pipeline processor 容错多管管线处理器
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291240
H. Mori, M. Uehara
{"title":"Fault tolerant multicube pipeline processor","authors":"H. Mori, M. Uehara","doi":"10.1109/ICWSI.1994.291240","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291240","url":null,"abstract":"This paper describes the architecture of fault tolerant pipeline processors. It uses multicube interconnection and voting based on cell reliability. Our architecture, featuring majority voting of results and reliability assessment to cells, ensures higher performance over conventional approaches in fault tolerance.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126822015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test vehicle for a wafer-scale thermal pixel scene simulator 测试车辆的晶圆规模热像素场景模拟器
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291266
G. Chapman, L. Carr, M. Syrzycki, B. Dufort
{"title":"Test vehicle for a wafer-scale thermal pixel scene simulator","authors":"G. Chapman, L. Carr, M. Syrzycki, B. Dufort","doi":"10.1109/ICWSI.1994.291266","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291266","url":null,"abstract":"A chip sized test vehicle has been created to experiment with two wafer scale thermal pixel displays: a Thermal Pixel Dynamic Scene Simulator and a Visual-to-Thermal Converter. The 4.7/spl times/4.7 mm device contains a 2/spl times/4 array of micromachined thermal pixels, optical detectors, A/D converters, digital pixel control circuitry, and laser links for interconnection. Laser produced defect avoidance schemes allowed testing and harvesting for global redundancy of the control circuitry and local transducer substitution. Also the laser linked signal buses flexibility were used to arrange the chip in different thermal pixel display configurations. Two chips were laser interconnected, one as fabricated and another where anisotropic etching had created a suspended plate holding the polysilicon resistor thermal pixels. From the electrical and laser interconnection points of operation there was no difference between the etched and unetched circuits.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"938 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132415863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Harvest model of an integrated hierarchical-bus architecture 集成层次总线体系结构的收获模型
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291262
R. Kermouche, Y. Savaria, D. Audet
{"title":"Harvest model of an integrated hierarchical-bus architecture","authors":"R. Kermouche, Y. Savaria, D. Audet","doi":"10.1109/ICWSI.1994.291262","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291262","url":null,"abstract":"This paper presents a new approach to model the yield of a fault-tolerant hierarchical-bus structure, based on the expected value of the number of functional processors. With this method, easily computable mathematical expressions were obtained. Also, a defect tolerant communication network structure is proposed and analyzed in terms of additional hardware cost versus spares allocation. Assuming the network was successfully repaired, global reconfiguration of defective processing modules is then supported. Otherwise some graceful degradation would result. The results obtained, in terms of optimal distribution of spares in the communication network, show that complete duplication is not cost effective. However, redundancy can be added to the uppermost levels of the hierarchical tree in a very effective manner. Two harvest formulas were obtained; the first is an easily computed lower bound, and the second is exact according to the assumed defect density.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130498186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An efficient method to reduce roundoff error in matrix multiplication with algorithm-based fault tolerance 基于容错算法降低矩阵乘法舍入误差的有效方法
Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI: 10.1109/ICWSI.1994.291235
Qihong Zhang, J.H. Kim
{"title":"An efficient method to reduce roundoff error in matrix multiplication with algorithm-based fault tolerance","authors":"Qihong Zhang, J.H. Kim","doi":"10.1109/ICWSI.1994.291235","DOIUrl":"https://doi.org/10.1109/ICWSI.1994.291235","url":null,"abstract":"Algorithm-Based Fault Tolerance (ABFT) schemes have been proposed by a number of researchers recently. Although all errors can be theoretically detected and corrected by using these techniques, some practical problems, especially the roundoff errors, degrade the performance drastically. In this paper, we proposed a new scheme called Extended Mantissa Checksum (EMC) test in which the mantissa of the product of two input matrices are divided into two sections and extended for faulty detection and correction. Using this scheme, the number of undetected errors and false alarms are decreased largely and the error coverage is improved significantly. In addition, the time latency is short and the hardware overhead is small compared with other schemes.<<ETX>>","PeriodicalId":183733,"journal":{"name":"Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128325023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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