Cycles analysis for testability of WSI sequential architectures

Abstract

Testability analysis can he performed through classification of all possible simple interconnection topologies, definition of testability conditions on the functions performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feed-forward architectures are studied. Application of such approach to irregular architectures with cycles (signal feedbacks) is presented in this paper.<>