Integration scale increase of processor-arrays by using hierarchical redundancy

Abstract

This paper specifies the relationships between WSI array structures and the maximum WSI integration scales possible when using hierarchical k-out-of-n redundancy configurations having expanded hierarchical levels. An estimate using five kinds of one-dimensional/two-dimensional array-connection models indicates that four-level redundancy configurations can increase the maximum possible integration scales 4 to 64 times over that achieved by single-level configurations according to the complexity of the array-connections. This feature is based on the distribution of defect-tolerance load into the hierarchical structures enhanced by expanding the hierarchical levels.<>