利用分层冗余提高处理器阵列集成规模

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI) Pub Date : 1994-01-19 DOI:10.1109/ICWSI.1994.291241

N. Tsuda

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引用次数: 1

摘要

本文详细说明了WSI阵列结构和最大WSI集成尺度之间的关系，当使用具有扩展层次级别的分层k-out- n冗余配置时，可能的WSI集成尺度。利用五种一维/二维阵列连接模型进行的估计表明，根据阵列连接的复杂性，四级冗余配置可以将最大可能集成规模提高到单级配置的4 ~ 64倍。该特性是基于缺陷容忍负荷在分层结构中的分布，通过扩展分层层次来增强。

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Integration scale increase of processor-arrays by using hierarchical redundancy

This paper specifies the relationships between WSI array structures and the maximum WSI integration scales possible when using hierarchical k-out-of-n redundancy configurations having expanded hierarchical levels. An estimate using five kinds of one-dimensional/two-dimensional array-connection models indicates that four-level redundancy configurations can increase the maximum possible integration scales 4 to 64 times over that achieved by single-level configurations according to the complexity of the array-connections. This feature is based on the distribution of defect-tolerance load into the hierarchical structures enhanced by expanding the hierarchical levels.<>

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Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)

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